FWLXT9784BE.A3 Cortina Systems Inc, FWLXT9784BE.A3 Datasheet - Page 27

no-image

FWLXT9784BE.A3

Manufacturer Part Number
FWLXT9784BE.A3
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of FWLXT9784BE.A3

Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FWLXT9784BE.A3
Manufacturer:
Intel
Quantity:
25
Part Number:
FWLXT9784BE.A3
Manufacturer:
Intel
Quantity:
10 000
Datasheet
Table 8. RMII Mode Signal Descriptions (Continued)
Table 9. SMII Mode Signal Descriptions
W3
T1
R3
M1
H1
F2
D1
B2
L1
V3
U1
P3
N1
G1
G2
C1
C2
W2
T2
R2
M2
J3
F3
E3
B3
L1
1. Refer to
1. Refer to
Ball ID
Ball ID
Table 1 on page 11
Table 1 on page 11
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
SYNC
Signal Name
TXEN0
TXEN1
TXEN2
TXEN3
TXEN4
TXEN5
TXEN6
TXEN7
TXD4
Signal Name
for Signal Type Definitions.
for Signal Type Definitions.
Type
O
I
I
1
Type
I
I
Receive Data and Control, Ports 0-7. Receive data stream,
that contains all of the information found on the receive path of
the standard MII.
Transmit Data and Control, Ports 0-7. Transmit data stream,
that contains all of the information found on the transmit path
of the standard MII.
Synchronization. Defines the SMII segment boundaries.
1
Transmit Enable, Ports 0-7. The transmit enable
signal indicates to the LXT9784 that valid data is
present on the TXD[1:0] pins of the appropriate port.
Fifth Transmit Data Bit. When the LXT9784 is in a
4B5B by-pass mode, the TXD4 pin is used as the fifth
transmit data bit of all eight ports. This signal allows for
limited symbol interface functionality.
Low-Power Octal PHY — LXT9784
Signal Description
Signal Description
27

Related parts for FWLXT9784BE.A3