DJLXT901LC.E2 S E001 Intel, DJLXT901LC.E2 S E001 Datasheet - Page 42

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DJLXT901LC.E2 S E001

Manufacturer Part Number
DJLXT901LC.E2 S E001
Description
Manufacturer
Intel
Datasheet

Specifications of DJLXT901LC.E2 S E001

Lead Free Status / RoHS Status
Not Compliant
LXT901/907 — Universal 10BASE-T and AUI Transceivers
4.4
42
TPIP/TPIN
or DIP/DIN
NOTE:
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
TPIP/TPIN
or DIP/DIN
Figure 37. Mode 4 RCLK/Start-of-Frame Timing
Figure 38. Mode 4 RCLK/End-of-Frame Timing
RCLK
RXD
RCLK
CD
RXD
CD
Timing Diagrams for Mode 4 (MD1 = High, MD0 = High)
Figures 37 - 42
1
1
t
CD
0
0
1
1
t
RD
1
0
0
t
DATA
0
1
1
1
0
0
1
0
1
0
1
0
1
0
0
t
1
RDS
1
1
t
1
CDOFF
0
0
0
1
0
1
0
t
RDH
0
1
0
0
0
1
1
0
0
1
Rev. Date: June 19, 2001
1
1
Document #: 249097
1
Revision #: 002
Datasheet
0
1

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