HY82563EB S L7WG Intel, HY82563EB S L7WG Datasheet - Page 12

• Manufacturer Part Number: HY82563EB S L7WG
• Manufacturer: Intel

Specifications of HY82563EB S L7WG

• Lead Free Status / RoHS Status: Compliant

82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon
3.2
3.3
6
Table 1.
Table 2.
Note: For normal operation, the MDIO interface is strapped externally according to
Shared PHY Pins
Shared PHY Pins
MDIO Interface
MDIO Interface Pins
MDIO being an in-band operation.
PHY_REF
MDC
MDIO
MDIO_ADD[0]
MDIO_ADD[1]
MDIO_ADD[2]
MDIO_ADD[3]
Signal Name
Signal Name
Pin
50
77
76
78
79
18
19
Pin
Type
B
Type
I (T)
I/O
PU
I (T)
Sub-
Type
B
TTL
TTL6
TTL
Sub-
Type
PHY Reference
External 4.99 KΩ ± 1% resistor connection to VSS.
Management Data Clock
This signal is received from the 631xESB/632xESB as a clock
timing reference for information transfer on the MDIO signal. It is
not required to be a continuous signal and can be frozen when
no management data is transferred. This signal has a maximum
operating frequency of 2.5 MHz.
A 1 - 10 KΩ ± 5% pull-down resistor should be connected to this
pin.
Management Data Input/Output
Bi-directional data signal of the management data interface.
This pin has an internal pull-up. This signal can be left
disconnected (or pulled up) if not used.
Bits 4:1 of MDIO address
These bits are latched at the assertion of PHY_PWR_GOOD or
the de-assertion of PHY_RESET_N or PHY_SLEEP. They set
the MDIO address as follows:
A 1 -10 kΩ ± 5% pull-down resistor should be connected to each
of these pins.
• bit 1 = MDIO_ADD[0]
• bit 2 = MDIO_ADD[1]
• bit 3 = MDIO_ADD[2]
• bit 4 = MDIO_ADD[3]
Description
Description
Table 39
due to