SI3210M-FTR Silicon Laboratories Inc, SI3210M-FTR Datasheet - Page 93
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SI3210M-FTR
Manufacturer Part Number
SI3210M-FTR
Description
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI3210M-FTR.pdf
(138 pages)
Specifications of SI3210M-FTR
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Register 52. FSK Data
Reset settings = 0000_0000
Register 63. Loop Closure Debounce Interval
Reset settings = 0011_0010 (revision C); 0101_0100 (subsequent revisions)
Name
Name
Bit
7:1
Bit
7:0
Type
Type
0
Bit
Bit
Reserved
LCD[7:0]
FSKDAT
Name
Name
D7
D7
Read returns zero.
FSK Data.
When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6), this
bit serves as the buffered input for FSK generation bit stream data.
Loop Closure Debounce Interval for Automatic Ringing.
This register sets the loop closure debounce interval for the ringing silent period when
using automatic ringing cadences. The value may be set between 0 ms (0x00) and
159 ms (0x7F) in 1.25 ms steps.
D6
D6
D5
D5
Rev. 1.45
D4
D4
LCD[7:0]
Function
Function
D3
D3
D2
D2
Si3210/Si3211
D1
D1
FSKDAT
R/W
D0
D0
93
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