82V1074PF IDT, Integrated Device Technology Inc, 82V1074PF Datasheet - Page 65

• Manufacturer Part Number: 82V1074PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V1074PF

• Number Of Channels: 4
• On-hook Transmission: Yes
• Polarity Reversal: Yes
• On-chip Ring Relay Driver: Yes
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TQFP
• Operating Temperature Classification: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Operating Current: 95mA
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Lead Free Status / RoHS Status: Not Compliant

5.3.2
RSLIC & CODEC CHIPSET
GREG1: PLL Power Down, Read/Write (20H/A0H)
GREG2: Reserved.
GREG3: PCM Configuration, Read/Write (22H/A2H)
In the following global registers and local registers lists, it should be noted that:
1. R/W = 0, Read command. R/W = 1, Write command.
2. The reserved bit(s) in the register must be filled in ‘0’ in write operation and will be ignored in read operation.
3. The global or local registers described below are available for both MPI and GCI modes except for those with special statement.
GLOBAL REGISTERS LIST
PLL_PD
Other bits in this register are reserved for future use.
This register is reserved for future use.
L_CODE
A/µ
DBL_CLK
TR_SLOPE[1:0] Transmit and receive slope selection. The TR_SLOPE[1:0] bits are used for MPI mode only.
PCM_OFT[2:0]
Command
Command
I/O data
I/O data
L_CODE
PLL_PD
Power down the internal PLL block (refer to
PLL_PD = 0:
PLL_PD = 1:
Voice data code (8-bit, A/µ-law compressed code or 16-bit linear code) selection
L_CODE = 0:
L_CODE = 1:
Select the PCM law
A/µ = 0:
A/µ = 1:
Clock mode (single or double) selection. This bit is used for MPI mode only.
DBL_CLK = 0:
DBL_CLK = 1:
TR_SLOPE[1:0]=00: transmits data on the rising edges of BCLK, receives data on the falling edges of BCLK (default);
TR_SLOPE[1:0]=01: transmits data on the rising edges of BCLK, receives data on the rising edges of BCLK;
TR_SLOPE[1:0]=10: transmits data on the falling edges of BCLK, receives data on the falling edges of BCLK;
TR_SLOPE[1:0]=11: transmits data on the falling edges of BCLK, receives data on the rising edges of BCLK;
Note: Please refer to IDT82V1074 Application Note (AN-380) for details on the effective edge selection of the BCLK
signal with great jitter.
PCM timing offset selection. The PCM transmit/receive time slot can be offset from FSC by 0 to 7 BCLK periods. The
PCM_OFT[2:0] bits are used for MPI mode only.
PCM_OFT[2:0]=000: offset from FSC by 0 BCLK period (default);
PCM_OFT[2:0]=001: offset from FSC by 1 BCLK period;
PCM_OFT[2:0]=010: offset from FSC by 2 BCLK periods;
PCM_OFT[2:0]=011: offset from FSC by 3 BCLK periods;
PCM_OFT[2:0]=100: offset from FSC by 4 BCLK periods;
PCM_OFT[2:0]=101: offset from FSC by 5 BCLK periods;
PCM_OFT[2:0]=110: offset from FSC by 6 BCLK periods;
PCM_OFT[2:0]=111: offset from FSC by 7 BCLK periods.
R/W
R/W
b7
b7
A/
b6
b6
0
0
µ
the internal PLL block is powered up (default);
the internal PLL block is powered down.
compressed code is selected (default);
linear code is selected.
µ-law is selected;
A-law is selected (default).
single clock is selected (default);
double clock is selected.
DBL_CLK
b5
b5
1
1
65
b4
b4
0
0
TR_SLOPE[1:0]
“6.2 PLL Power Down” on page 90
Reserved
b3
b3
0
0
b2
b2
0
0
IDT82V1671/IDT82V1671A, IDT82V1074
PCM_OFT[2:0]
for details).
b1
b1
0
1
b0
b0
0
0