XC6SLX16-2CSG324I Xilinx Inc, XC6SLX16-2CSG324I Datasheet - Page 6
![FPGA, SPARTAN-6 LX, 14K, 324CSGBGA](/photos/18/28/182878/xc6slx45-2csg324c_sml.jpg)
XC6SLX16-2CSG324I
Manufacturer Part Number
XC6SLX16-2CSG324I
Description
FPGA, SPARTAN-6 LX, 14K, 324CSGBGA
Manufacturer
Xilinx Inc
Series
Spartan® 6 LXr
Specifications of XC6SLX16-2CSG324I
No. Of Logic Blocks
2278
No. Of Macrocells
14579
Family Type
Spartan-6
No. Of Speed Grades
2
No. Of I/o's
232
Clock Management
DCM, PLL
I/o Supply Voltage
3.3V
Total Ram Bits
589824
Number Of Logic Elements/cells
14579
Number Of Labs/clbs
1139
Number Of I /o
232
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
324-LFBGA, CSPBGA
Core Supply Voltage Range
1.14V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC6SLX16-2CSG324I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Block RAM
Every Spartan-6 FPGA has between 12 and 268 dual-port block RAMs, each storing 18 Kb. Each block RAM has two
completely independent ports that share only the stored data.
Synchronous Operation
Each memory access, whether read or write, is controlled by the clock. All inputs, data, address, clock enables, and write
enables are registered. The data output is always latched, retaining data until the next operation. An optional output data
pipeline register allows higher clock rates at the cost of an extra cycle of latency.
During a write operation in dual-port mode, the data output can reflect either the previously stored data, the newly written
data, or remain unchanged.
Programmable Data Width
•
•
•
Memory Controller Block
Most Spartan-6 devices include dedicated memory controller blocks (MCBs), each targeting a single-chip DRAM (either
DDR, DDR2, DDR3, or LPDDR), and supporting access rates of up to 800 Mb/s.
The MCB has dedicated routing to predefined FPGA I/Os. If the MCB is not used, these I/Os are available as general
purpose FPGA I/Os. The memory controller offers a complete multi-port arbitrated interface to the logic inside the
Spartan-6 FPGA. Commands can be pushed, and data can be pushed to and pulled from independent built-in FIFOs, using
conventional FIFO control signals. The multi-port memory controller can be configured in many ways. An internal 32-, 64-,
or 128-bit data interface provides a simple and reliable interface to the MCB.
The MCB can be connected to 4-, 8-, or 16-bit external DRAM. The MCB, in many applications, provides a faster DRAM
interface compared to traditional internal data buses, which are wider and are clocked at a lower frequency. The FPGA logic
interface can be flexibly configured irrespective of the physical memory device. The MCB functionality is not supported in the
-3N speed grade.
Digital Signal Processing—DSP48A1 Slice
DSP applications use many binary multipliers and accumulators, best implemented in dedicated DSP slices. All
Spartan-6 FPGAs have many dedicated, full-custom, low-power DSP slices, combining high speed with small size, while
retaining system design flexibility.
Each DSP48A1 slice consists of a dedicated 18 × 18 bit two's complement multiplier and a 48-bit accumulator, both capable
of operating at up to 390 MHz. The DSP48A1 slice provides extensive pipelining and extension capabilities that enhance
speed and efficiency of many applications, even beyond digital signal processing, such as wide dynamic bus shifters,
memory address generators, wide bus multiplexers, and memory-mapped I/O register files. The accumulator can also be
used as a synchronous up/down counter. The multiplier can perform barrel shifting.
DS160 (v1.7) March 21, 2011
Preliminary Product Specification
Each port can be configured as 16K × 1, 8K × 2, 4K × 4, 2K × 9 (or 8), 1K × 18 (or 16), or 512 x 36 (or 32).
The x9, x18, and x36 configurations include parity bits. The two ports can have different aspect ratios.
Each block RAM can be divided into two completely independent 9 Kb block RAMs that can each be configured to any
aspect ratio from 8K x 1 to 512 x 18, with 256 x 36 supported in simple dual-port mode.
www.xilinx.com
Spartan-6 Family Overview
6