XC6SLX150T-2FGG484C Xilinx Inc, XC6SLX150T-2FGG484C Datasheet - Page 72
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XC6SLX150T-2FGG484C
Manufacturer Part Number
XC6SLX150T-2FGG484C
Description
FPGA, SPARTAN-6 LXT, 147K, 484FGGBGA
Manufacturer
Xilinx Inc
Series
Spartan® 6 LXTr
Specifications of XC6SLX150T-2FGG484C
No. Of Logic Blocks
23038
No. Of Macrocells
147443
Family Type
Spartan-6
No. Of Speed Grades
2
Total Ram Bits
4939776
No. Of I/o's
296
Clock Management
DCM, PLL
I/o Supply Voltage
3.3V
Number Of Logic Elements/cells
147443
Number Of Labs/clbs
11519
Number Of I /o
296
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-BBGA
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC6SLX150T-2FGG484C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 76: Package Skew (Cont’d)
Table 77: Sample Window
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Notes:
1.
2.
Notes:
1.
2.
3.
T
T
T
PKGSKEW
SAMP
SAMP_BUFIO2
These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from Pad to Ball.
Some of these devices are available in both Pb and Pb-free (additional G) packages as standard ordering options.
LXT devices are not available with a -1L speed grade.
This parameter indicates the total sampling error of Spartan-6 FPGA DDR input registers, measured across voltage, temperature, and process. The
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 DCM jitter
- DCM accuracy (phase offset)
- DCM phase shift resolution
These measurements do not include package or clock tree skew.
This parameter indicates the total sampling error of Spartan-6 FPGA DDR input registers, measured across voltage, temperature, and process. The
characterization methodology uses the BUFIO2 clock network and IODELAY2 to capture the DDR input registers’ edges of operation. These
measurements do not include package or clock tree skew.
Symbol
Symbol
Sampling Error at Receiver Pins
Sampling Error at Receiver Pins using
BUFIO2
Package Skew
(3)
Description
Description
(1)
(2)
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
XC6SLX150
XC6SLX150T
Device
All
All
Device
(1)
510
430
-3
Package
FG(G)484
FG(G)676
FG(G)900
FG(G)484
FG(G)676
FG(G)900
CSG484
CSG484
510
430
-3N
Speed Grade
(2)
530
450
-2
Value
103
115
121
141
120
84
83
88
740
590
-1L
Units
ps
ps
ps
ps
ps
ps
ps
ps
Units
ps
ps
72