XCF16PVOG48C Xilinx Inc, XCF16PVOG48C Datasheet - Page 35

• Manufacturer Part Number: XCF16PVOG48C
• Description: PROM, PLATFORM FLASH, 16MBIT, 48TSOP
• Manufacturer: Xilinx Inc

Specifications of XCF16PVOG48C

• Memory Type: Flash
• Memory Size: 16Mbit
• Clock Frequency: 50MHz
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Programmable Type: In System Programmable
• Voltage - Supply: 1.65 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TFSOP (0.472", 12.0mm Width)
• Interface Type: Serial, Parallel, JTAG
• Supply Voltage Range: 1.65V To 2V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1456-5

Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
DS123 (v2.18) May 19, 2010
Product Specification
10/26/09
05/19/10
Date
R
Version
(Cont’d)
2.17
2.18
• Updated text in second and third bulleted items in
• Removed all references to 1.5V operation from
Removed ordering codes for discontinued VO48 package from
XCN09030). Added note to
XCN08005).
Conditions," page
page
26.
14,
www.xilinx.com
Platform Flash In-System Programmable Configuration PROMs
"DC Characteristics Over Operating Conditions," page
Figure 15
and
Figure 16
Revision
"Features," page
describing traceability code in top mark (see
"Initiating FPGA Configuration," page
"Valid Ordering Combinations"
1,
"Recommended Operating
15, and
Table 13,
10.
(see
35