MCP4716A0T-E/CH Microchip Technology, MCP4716A0T-E/CH Datasheet - Page 13
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MCP4716A0T-E/CH
Manufacturer Part Number
MCP4716A0T-E/CH
Description
Single, 10-bit NV DAC With Ext Vref And I2C Interface 6 SOT-23 T/R
Manufacturer
Microchip Technology
Series
-r
Datasheet
1.MCP4706A0T-ECH.pdf
(86 pages)
Specifications of MCP4716A0T-E/CH
Number Of Converters
1
Conversion Rate
1
Resolution
10 bit
Interface Type
I2C
Settling Time
6 us
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SOT-23-6
Maximum Power Dissipation
452 mW
Minimum Operating Temperature
- 40 C
Supply Current
210 uA
Number Of Bits
10
Data Interface
EEPROM, I²C, Serial
Voltage Supply Source
Single Supply
Power Dissipation (max)
452mW
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Number Of Outputs And Type
*
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCP4716A0T-E/CH
Manufacturer:
Microchip
Quantity:
11 500
Part Number:
MCP4716A0T-E/CH
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
TABLE 1-3:
© 2011 Microchip Technology Inc.
I
Note 1:
2
Param.
C AC Characteristics
No.
111
2:
3:
4:
5:
6:
7:
8:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
A fast-mode (400 kHz) I
requirement t
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line.
T
the SCL line is released.
The MCP47X6 device must provide a data hold time to bridge the undefined part between V
the falling edge of the SCL signal. This specification is not a part of the I
in order to ensure that the output data will meet the setup and hold specifications for the receiving device.
Use C
Not Tested. This parameter ensured by characterization.
A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the
I
affected.
Ensured by the T
The specification is not part of the I 2 C specification. T
2
R
C bus line. If this parameter is too long, the Data Input Setup (T
Sym
max.+t
T
SP
b
I
2
in pF for the calculations.
C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
Data Input: This parameter must be longer than t
Data Output: This parameter is characterized, and tested indirectly by testing T
SU;DAT
Characteristic
Input filter spike
suppression
(SDA and SCL)
SU;DAT
AA
= 1000 + 250 = 1250 ns (according to the standard-mode I
3.4 MHz specification test.
≥ 250 ns must then be met. This will automatically be the case if the device does not
2
C-bus device can be used in a standard-mode (100 kHz) I
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
Operating Voltage V
1.7 MHz mode
3.4 MHz mode
100 kHz mode
400 kHz mode
50 (typ)
10 (typ)
10 (typ)
—
DD
range is described in
Min
—
—
—
—
—
—
—
—
AA
MCP4706/4716/4726
= T
–40°C ≤ T
SP
HD:DAT
.
Max
50
50
10
10
—
—
—
—
SU:DAT
+ T
A
≤ +125°C (Extended)
FSDA
2
Units
) or Clock Low time (T
C specification, but must be tested
ns
ns
ns
ns
ns
ns
ns
ns
Electrical characteristics
2
(or T
C bus specification) before
NXP Spec states N.A.
Spike suppression
Spike suppression
Standard Mode,
(Not Applicable)
Fast Mode
High Speed Mode 1.7
High Speed Mode 3.4
RSDA
2
C-bus system, but the
).
Conditions
DS22272A-page 13
AA
IH
parameter.
LOW
and V
) can be
IL
of