PIC12F615-H/SN Microchip Technology, PIC12F615-H/SN Datasheet - Page 16
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC12F615-H/SN
Manufacturer Part Number
PIC12F615-H/SN
Description
1.75KB Flash, 64B RAM, 6 I/O, 8MHz Internal Oscillator 8 SOIC 3.90mm (.150") TUB
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Specifications of PIC12F615-H/SN
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC12F615-H/SN
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC12F609/615/617/12HV609/615
TABLE 2-3:
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
Note
DS41302D-page 16
Addr
1:
2:
3:
4:
INDF
OPTION_RE
G
PCL
STATUS
FSR
TRISIO
PCLATH
INTCON
PIE1
PCON
OSCTUNE
WPU
IOC
ANSEL
Name
(2)
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch
exists.
TRISIO3 always reads as ‘1’ since it is an input only pin.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
GPPU
IRP
Bit 7
GIE
—
—
—
—
—
—
—
—
(1)
INTEDG
RP1
Bit 6
PEIE
—
—
—
—
—
—
—
—
(1)
TRISIO5
WPU5
T0CS
IOC5
Bit 5
T0IE
RP0
—
—
—
—
—
TRISIO4
WPU4
TUN4
T0SE
INTE
IOC4
Bit 4
TO
—
—
—
Write Buffer for upper 5 bits of Program Counter
TRISIO3
CMIE
TUN3
ANS3
GPIE
IOC3
Bit 3
PSA
PD
—
—
(4)
TRISIO2
WPU2
TUN2
IOC2
Bit 2
T0IF
PS2
—
—
—
Z
TRISIO1
WPU1
TUN1
ANS1
IOC1
Bit 1
INTF
POR
PS1
DC
—
2010 Microchip Technology Inc.
TRISIO0
TMR1IE
GPIF
WPU0
TUN0
ANS0
IOC0
Bit 0
BOR
PS0
C
(3)
xxxx xxxx 25, 116
1111 1111 19, 116
0000 0000 25, 116
0001 1xxx 18, 116
xxxx xxxx 25, 116
--11 1111 44, 116
---0 0000 25, 116
0000 0000 20, 116
---- 0--0 21, 116
---- --qq 23, 116
---0 0000 41, 116
--11 -111 46, 116
--00 0000 46, 116
---- 1-11 45, 117
POR, BOR
Value on
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