PIC12F635T-I/MD Microchip Technology, PIC12F635T-I/MD Datasheet - Page 4
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PIC12F635T-I/MD
Manufacturer Part Number
PIC12F635T-I/MD
Description
1.75 KB Flash, 64 RAM, 6 I/O 8 DFN 4x4mm T/R
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Specifications of PIC12F635T-I/MD
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
5
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164326 - MODULA SKT PM3 20QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNXLT08DFN - SOCKET TRANSITION ICE 8DFN
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC12F635
4.
3. Module: Wake-up Reset (WUR)
DS80203K-page 4
If periodic interrupts are occurring in addition to
the EEIF interrupts, then use a secondary flag to
sense write completion. The secondary flag is
set whenever data EEPROM writes are active. A
data EEPROM write completion is indicated
when the secondary flag is set and the WR flag
is clear.
Affected Silicon Revisions
If a Wake-up Reset occurs when the Wake-up
Reset (WURE) and Power-up Timer (PWTRE)
Configuration bits are enabled, then there will not
be a 72 ms time delay from the Power-up Timer, as
expected.
Work around
None.
Affected Silicon Revisions
A1
A1
X
X
B2
B2
B3
B3
4. Module: Internal/External Clock Switch
If a Wake-up Reset occurs when the Wake-up
Reset (WURE) and Internal/External Clock Switch
Over (IESO) Configuration bits are enabled and
there is no external clock applied to the chip when
in the XT/HS configurations, the processor will
remain in Reset and not begin executing
instructions.
Work around
There is no work around for revision A silicon for
this errata. However, this issue was corrected for
revision B silicon. If a Wake-up Reset occurs when
the Wake-up Reset and Internal/External Clock
Switch Over Configuration bits are enabled in
revision B silicon and Wake-up Reset occurs, the
chip will wake up and reset as expected.
Affected Silicon Revisions
A1
X
B2
Over (IESO)
B3
© 2009 Microchip Technology Inc.