PIC12F675T-I/MF Microchip Technology, PIC12F675T-I/MF Datasheet - Page 105
PIC12F675T-I/MF
Manufacturer Part Number
PIC12F675T-I/MF
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,8PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F629T-ISN.pdf
(136 pages)
2.PIC12F629T-ISN.pdf
(8 pages)
3.PIC12F629T-ISN.pdf
(24 pages)
Specifications of PIC12F675T-I/MF
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNXLT08DFN - SOCKET TRANSITION ICE 8DFNAC164032 - ADAPTER PICSTART PLUS 8DFN/DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC12F675-I/MFTR
PIC12F675T-I/MFTR
PIC12F675T-I/MFTR
PIC12F675T-I/MFTR
PIC12F675T-I/MFTR
FIGURE 12-11:
TABLE 12-10: PIC12F675 A/D CONVERSION REQUIREMENTS (SLEEP MODE)
2010 Microchip Technology Inc.
130
130
131
132
134
Note 1: ADRES register may be read on the following T
Param
No.
Note 1: If the A/D clock source is selected as RC, a time of T
A/D DATA
*
†
SAMPLE
A/D CLK
2: See Section 7.1 “A/D Configuration and Operation” for minimum conditions.
BSF ADCON0, GO
ADRES
These parameters are characterized but not tested.
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
ADIF
GO
Q4
T
T
T
T
T
AD
CNV
ACQ
SLEEP instruction to be executed.
AD
Sym
GO
134
132
A/D Clock Period
A/D Internal RC
Oscillator Period
Conversion Time
(not including
Acquisition Time)
Acquisition Time
Q4 to A/D Clock
Start
PIC12F675 A/D CONVERSION TIMING (SLEEP MODE)
Characteristic
(T
OSC
/2 + T
(1)
CY
(Note 2)
9
)
(1)
Min
3.0*
3.0*
2.0*
1.6
—
—
5*
OLD_DATA
SAMPLING STOPPED
8
T
OSC
7
Typ†
11.5
131
6.0
4.0
/2 + T
CY
—
—
11
—
CY
cycle.
6
is added before the A/D clock starts. This allows the
CY
130
Max
9.0*
6.0*
3
—
—
—
—
—
—
Units
2
T
s
s
s
s
s
s
—
AD
PIC12F629/675
1
V
V
ADCS<1:0> = 11 (RC mode)
At V
At V
The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1 LSb (i.e.,
4.1 mV @ 4.096V) from the last
sampled voltage (as stored on
C
If the A/D clock source is selected
as RC, a time of T
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
REF
REF
HOLD
DD
DD
3.0V
full range
).
0
= 2.5V
= 5.0V
NEW_DATA
Conditions
1 T
DONE
DS41190G-page 105
CY
1 T
CY
CY
is added