PIC16F1526-E/PT Microchip Technology, PIC16F1526-E/PT Datasheet - Page 281

• Manufacturer Part Number: PIC16F1526-E/PT
• Description: 64-pin, 14KB Flash, 768B RAM, 10-bit ADC, 10xCCP, 2xSPI, 2xMI2C, 2xEUSART, 2.3V-
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1526-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TQFP
• Processor Series: PIC16F
• Core: PIC
• Data Ram Size: 768 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 9
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.5.2
The following bits are used to configure the EUSART
for Synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXxSTA register configures
the device for synchronous operation. Clearing the
CSRC bit of the TXxSTA register configures the device as
a slave. Clearing the SREN and CREN bits of the
RCxSTA register ensures that the device is in the
Transmit mode, otherwise the device will be configured to
receive. Setting the SPEN bit of the RCxSTA register
enables the EUSART. If the RXx/DTx or TXx/CKx pins
are shared with an analog peripheral the analog I/O
functions must be disabled by clearing the corresponding
ANSEL bits.
RXx/DTx and TXx/CKx pin output drivers must be
disabled by setting the corresponding TRIS bits.
22.5.2.1
The operation of the Synchronous Master and Slave
modes
“Synchronous Master
case of the Sleep mode.
 2011 Microchip Technology Inc.
are
SYNCHRONOUS SLAVE MODE
EUSART Synchronous Slave
Transmit
identical
Transmission”) , except in the
(see
Section 22.5.1.3
Preliminary
If two words are written to the TXxREG and then the
SLEEP instruction is executed, the following will occur:
1.
2.
3.
4.
5.
22.5.2.2
1.
2.
3.
4.
5.
6.
7.
8.
The first character will immediately transfer to
the TSR register and transmit.
The second word will remain in TXxREG
register.
The TXxIF bit will not be set.
After the first character has been shifted out of
TSR, the TXxREG register will transfer the
second character to the TSR and the TXxIF bit
will now be set.
If the PEIE and TXxIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
Set the SYNC and SPEN bits and clear the
CSRC bit.
Set the RXx/DTx and TXx/CKx TRIS controls to
‘1’.
Clear the CREN and SREN bits.
If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
TXxIE bit.
If 9-bit transmission is desired, set the TX9 bit.
Enable transmission by setting the TXEN bit.
If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
Start
Significant 8 bits to the TXxREG register.
PIC16(L)F1526/27
transmission
Synchronous Slave Transmission
Set-up:
by
writing
DS41458B-page 281
the
Least