PIC16F1526T-I/PT Microchip Technology, PIC16F1526T-I/PT Datasheet - Page 189

• Manufacturer Part Number: PIC16F1526T-I/PT
• Description: 64-pin, 14KB Flash, 768B RAM, 10-bit ADC, 10xCCP, 2xSPI, 2xMI2C, 2xEUSART, 2.3V-
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1526T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.2.3
When Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the CCPx module does not
assert control of the CCPx pin (see the CCPxCON
register).
20.2.4
When Special Event Trigger mode is chosen
(CCPxM<3:0> = 1011), the CCPx module does the
following:
• Resets Timer1/3/5
• Starts an ADC conversion if ADC is enabled
The CCPx module does not assert control of the CCPx
pin in this mode.
The Special Event Trigger output of the CCP occurs
immediately upon a match between the TMRxH,
TMRxL register pair and the CCPRxH, CCPRxL regis-
ter pair. The TMRxH, TMRxL register pair is not reset
until the next rising edge of the Timer1/3/5 clock. The
Special Event Trigger output starts an A/D conversion
(if the A/D module is enabled). This allows the
CCPRxH, CCPRxL register pair to effectively provide a
16-bit programmable period register for Timer1/3/5.
TABLE 20-4:
Refer to
more information.
 2011 Microchip Technology Inc.
Note 1: The Special Event Trigger from the CCP
PIC16(L)F1526/27
2: Removing
Section 16.2.5 “Special Event Trigger”
Device
SPECIAL EVENT TRIGGER
SOFTWARE INTERRUPT MODE
module does not set interrupt flag bit
TMRxIF of the PIRx register.
changing the contents of the CCPRxH
and CCPRxL register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1/3/5 Reset, will
preclude the Reset from occurring.
SPECIAL EVENT TRIGGER
the
match
CCP10
CCPx
condition
Preliminary
by
for
20.2.5
The Compare mode is dependent upon the system
clock (F
down during Sleep mode, the Compare mode will not
function properly during Sleep.
20.2.6
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see
more information.
OSC
PIC16(L)F1526/27
Section 12.1 “Alternate Pin Function”
COMPARE DURING SLEEP
ALTERNATE PIN LOCATIONS
) for proper operation. Since F
DS41458B-page 189
OSC
is shut
for