PIC16F1828-E/ML Microchip Technology, PIC16F1828-E/ML Datasheet - Page 338
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PIC16F1828-E/ML
Manufacturer Part Number
PIC16F1828-E/ML
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core 20 Q
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16F1824-ISL.pdf
(2 pages)
3.PIC16F1824-ISL.pdf
(419 pages)
4.PIC16F1824-ISL.pdf
(10 pages)
Specifications of PIC16F1828-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F722-ISS PDF datasheet
- PIC16F1824-ISL PDF datasheet #2
- PIC16F1824-ISL PDF datasheet #3
- PIC16F1824-ISL PDF datasheet #4
- Current page: 338 of 419
- Download datasheet (4Mb)
29.0
Each PIC16 instruction is a 14-bit word containing the
operation code (opcode) and all required operands.
The opcodes are broken into three broad categories.
• Byte Oriented
• Bit Oriented
• Literal and Control
The literal and control category contains the most var-
ied instruction word format.
Table 29-3
MPASM
All instructions are executed within a single instruction
cycle, with the following exceptions, which may take
two or three cycles:
• Subroutine takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two
• Program branching takes two cycles (GOTO, BRA,
• One additional instruction cycle will be used when
One instruction cycle consists of 4 oscillator cycles; for
an oscillator frequency of 4 MHz, this gives a nominal
instruction execution rate of 1 MHz.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
2010 Microchip Technology Inc.
cycles (RETURN, RETLW, RETFIE)
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)
any instruction references an indirect file register
and the file select register is pointing to program
memory.
TM
INSTRUCTION SET SUMMARY
assembler.
lists the instructions recognized by the
Preliminary
29.1
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
TABLE 29-1:
TABLE 29-2:
Field
Field
mm
DC
PC
TO
PD
PIC16(L)F1824/1828
W
C
b
d
n
Z
k
x
f
Register file address (0x00 to 0x7F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
Don’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
Destination select; d = 0: store result in
d = 1: store result in file register f.
Default is d = 1.
FSR or INDF number. (0-1)
Pre-post increment-decrement mode
selection
Program Counter
Time-out bit
Carry bit
Digit carry bit
Zero bit
Power-down bit
Read-Modify-Write Operations
OPCODE FIELD
DESCRIPTIONS
ABBREVIATION
DESCRIPTIONS
Description
Description
DS41419B-page 337
W
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