PIC16F1934T-I/MV Microchip Technology, PIC16F1934T-I/MV Datasheet - Page 315
![7KB Flash, 256B RAM, 256B EEPROM, LCD, 1.8-5.5V 40 UQFN 5x5x0.5mm T/R](/photos/16/12/161286/qfn44_sml.jpg)
PIC16F1934T-I/MV
Manufacturer Part Number
PIC16F1934T-I/MV
Description
7KB Flash, 256B RAM, 256B EEPROM, LCD, 1.8-5.5V 40 UQFN 5x5x0.5mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16LF1933-ISS.pdf
(508 pages)
3.PIC16LF1933-ISS.pdf
(46 pages)
4.PIC16F1936-ISS.pdf
(2 pages)
5.PIC16F1936-ISS.pdf
(10 pages)
6.PIC16F1936-ISS.pdf
(40 pages)
7.PIC16F1936-ISS.pdf
(30 pages)
8.PIC16F1936-ISS.pdf
(12 pages)
Specifications of PIC16F1934T-I/MV
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-UFQFN Exposed Pad
Processor Series
PIC16F
Core
PIC
Data Ram Size
256 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F1934T-I/MV
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F722-ISS PDF datasheet
- PIC16LF1933-ISS PDF datasheet #2
- PIC16LF1933-ISS PDF datasheet #3
- PIC16F1936-ISS PDF datasheet #4
- PIC16F1936-ISS PDF datasheet #5
- PIC16F1936-ISS PDF datasheet #6
- PIC16F1936-ISS PDF datasheet #7
- PIC16F1936-ISS PDF datasheet #8
- Current page: 315 of 508
- Download datasheet (5Mb)
24.4.2.3
The operation of the Synchronous Master and Slave
modes is identical (Section 24.4.1.5 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
TABLE 24-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
2009 Microchip Technology Inc.
BAUDCON
INTCON
PIE1
PIR1
RCREG
RCSTA
TRISC
TXSTA
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave
never Idle
Name
*
Reception.
Page provides register information.
EUSART Synchronous Slave
Reception
EUSART Receive Data Register
TMR1GIE
TMR1GIF
ABDOVF
TRISC7
CSRC
SPEN
Bit 7
RECEPTION
GIE
TRISC6
RCIDL
ADIE
PEIE
ADIF
Bit 6
RX9
TX9
TMR0IE
TRISC5
SREN
TXEN
RCIE
RCIF
Bit 5
—
TRISC4
Preliminary
CREN
SCKP
SYNC
INTE
Bit 4
TXIE
TXIF
TRISC3
ADDEN
SENDB
BRG16
SSPIE
SSPIF
IOCIE
24.4.2.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
Bit 3
PIC16F193X/LF193X
Set the SYNC and SPEN bits and clear the
CSRC bit.
Clear the ANSEL bit for both the CK and DT pins
(if applicable).
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TMR0IF
CCP1IE
CCP1IF
TRISC2
BRGH
FERR
Bit 2
—
Synchronous Slave Reception
Set-up:
TMR2IE
TMR2IF
TRISC1
OERR
TRMT
WUE
Bit 1
INTF
TMR1IE
TMR1IF
TRISC0
ABDEN
IOCIF
RX9D
TX9D
Bit 0
DS41364D-page 315
Register
on Page
294*
300
100
103
299
140
298
99
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