PIC16F707-I/MV Microchip Technology, PIC16F707-I/MV Datasheet - Page 44
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC16F707-I/MV
Manufacturer Part Number
PIC16F707-I/MV
Description
14KB Flash Program, MTouch, 32ch CSM, 1.8V-5.5V, 16MHz Internal Oscillator, 8b A
Manufacturer
Microchip Technology
Series
PIC® XLP™ mTouch™ 16Fr
Datasheet
1.PIC16F707-IPT.pdf
(284 pages)
Specifications of PIC16F707-I/MV
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Ram Size
363 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 14x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-UFQFN Exposed Pad
Processor Series
PIC16F
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (3Mb)
PIC16F707/PIC16LF707
4.5.3
The PIE2 register contains the interrupt enable bits, as
shown in Register 4-3.
REGISTER 4-3:
DS41418A-page 44
bit 7
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3-1
bit 0
TMR3GIE
R/W-0
TMR3GIE: Timer3 Gate Interrupt Flag bit
1 = Enable the Timer3 gate acquisition complete interrupt
0 = Disable the Timer3 gate acquisition complete interrupt
TMR3IE: Timer3 Overflow Interrupt Enable bit
1 = Enables the Timer3 overflow interrupt
0 = Disables the Timer3 overflow interrupt
TMRBIE: TimerB Overflow Interrupt Enable bit
1 = Enables the TimerB interrupt
0 = Disables the TimerB interrupt
TMRAIE: TimerA Overflow Interrupt Enable bit
1 = Enables the TimerA interrupt
0 = Disables the TimerA interrupt
Unimplemented: Read as '0'
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
PIE2 REGISTER
TMR3IE
R/W-0
PIE2 – PERIPHERAL INTERRUPT ENABLE REGISTER 2
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
TMRBIE
R/W-0
TMRAIE
Preliminary
R/W-0
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other
Resets
Note:
U-0
—
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
U-0
—
2010 Microchip Technology Inc.
U-0
—
CCP2IE
R/W-0
bit 0
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