PIC16F721-E/ML Microchip Technology, PIC16F721-E/ML Datasheet - Page 146
PIC16F721-E/ML
Manufacturer Part Number
PIC16F721-E/ML
Description
7 KB FLASH, 256 B SRAM, 18 I/O 20 QFN 4x4mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16LF720-ISS.pdf
(244 pages)
Specifications of PIC16F721-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16F/LF720/721
REGISTER 17-1:
DS41430A-page 146
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
WCOL
R/W-0
When enabled, these pins must be properly configured as input or output.
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
0 = No collision
SSPOV: Receive Overflow Indicator bit
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCK, SDO and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
SSPM<3:0>: Synchronous Serial Port mode Select bits
0000 = SPI Master mode, clock = F
0001 = SPI Master mode, clock = F
0010 = SPI Master mode, clock = F
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
SSPOV
R/W-0
software)
overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read
the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode the overflow
bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF
register.
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (SPI MODE)
W = Writable bit
‘1’ = Bit is set
SSPEN
R/W-0
R/W-0
CKP
OSC
OSC
OSC
/4
/16
/64
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPM3
R/W-0
SSPM2
R/W-0
2010 Microchip Technology Inc.
x = Bit is unknown
SSPM1
R/W-0
(1)
SSPM0
R/W-0
bit 0
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