PIC16F721T-I/SO Microchip Technology, PIC16F721T-I/SO Datasheet - Page 137

• Manufacturer Part Number: PIC16F721T-I/SO
• Description: 7 KB FLASH, 256 B SRAM, 18 I/O 20 SOIC .300in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.3.2.3
The operation of the Synchronous Master and Slave
modes is identical
Master
• Sleep
• CREN bit is always set, therefore the receiver is
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE interrupt enable bit
of the PIE1 register is set, the interrupt generated will
wake the device from Sleep and execute the next
instruction. If the GIE bit is also set, the program will
branch to the interrupt vector.
TABLE 16-9:
 2010 Microchip Technology Inc.
INTCON
PIE1
PIR1
RCREG
RCSTA
TRISC
TXSTA
Legend:
never Idle
Name
Reception”), with the following exceptions:
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous slave reception.
TMR1GIE
TMR1GIF
TRISC7
AUSART Synchronous Slave
Reception
SPEN
CSRC
Bit 7
GIE
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
(Section 16.3.1.4 “Synchronous
TRISC6
PEIE
ADIE
ADIF
Bit 6
RX9
TX9
TMR0IE
TRISC5
SREN
TXEN
RCIE
RCIF
Bit 5
AUSART Receive Data Register
TRISC4
CREN
SYNC
Bit 4
INTE
TXIE
TXIF
ADDEN
TRISC3
RABIE
SSPIE
SSPIF
Bit 3
—
TMR0IF
CCP1IE
CCP1IF
TRISC2
16.3.2.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
BRGH
FERR
Bit 2
Set the SYNC and SPEN bits and clear the
CSRC bit.
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Verify address detection is disabled by clearing
the ADDEN bit of the RCSTA register.
Set the CREN bit to enable reception.
The RCIF bit of the PIR1 register will be set
when reception is complete. An interrupt will be
generated if the RCIE bit of the PIE1 register
was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register.
PIC16F/LF720/721
TMR2IE
TMR2IF
TRISC1
OERR
TRMT
Bit 1
INTF
Synchronous Slave Reception Setup
TMR1IE
TMR1IF
TRISC0
RABIF
RX9D
TX9D
Bit 0
0000 000x
0000 0000
0000 0000
0000 0000
0000 000x
1111 1111
0000 -010
POR, BOR
Value on
DS41430A-page 137
0000 000x
0000 0000
0000 0000
0000 0000
0000 000x
1111 1111
0000 -010
Value on
all other
Resets