PIC16F722-E/ML Microchip Technology, PIC16F722-E/ML Datasheet - Page 50
![3.5 KB Flash, 1.8V-5.5V, 16 MHz Int. Osc 28 QFN 6x6mm TUBE](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16F722-E/ML
Manufacturer Part Number
PIC16F722-E/ML
Description
3.5 KB Flash, 1.8V-5.5V, 16 MHz Int. Osc 28 QFN 6x6mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.AC164112.pdf
(302 pages)
2.PIC16F722-ISS.pdf
(8 pages)
3.PIC16F722-ISS.pdf
(10 pages)
4.PIC16F722-ISS.pdf
(32 pages)
5.PIC16F722-ISS.pdf
(2 pages)
6.PIC16F722-ISS.pdf
(8 pages)
Specifications of PIC16F722-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- AC164112 PDF datasheet
- PIC16F722-ISS PDF datasheet #2
- PIC16F722-ISS PDF datasheet #3
- PIC16F722-ISS PDF datasheet #4
- PIC16F722-ISS PDF datasheet #5
- PIC16F722-ISS PDF datasheet #6
- Current page: 50 of 302
- Download datasheet (5Mb)
PIC16F72X/PIC16LF72X
4.5.5
The PIR2 register contains the interrupt flag bits, as
shown in Register 4-5.
REGISTER 4-5:
TABLE 4-1:
DS41341E-page 50
INTCON
OPTION_REG
PIE1
PIE2
PIR1
PIR2
Legend:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-1
bit 0
Name
U-0
—
- = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare and PWM.
PIR2 REGISTER
TMR1GIE
TMR1GIF
RBPU
Bit 7
GIE
Unimplemented: Read as ‘0’
CCP2IF: CCP2 Interrupt Flag bit
Capture Mode:
Compare Mode:
PWM mode:
Unused in this mode
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
U-0
—
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
INTEDG
PEIE
ADIE
ADIF
Bit 6
—
—
W = Writable bit
‘1’ = Bit is set
T0CS
U-0
RCIE
RCIF
Bit 5
T0IE
—
—
—
T0SE
Bit 4
INTE
TXIE
TXIF
—
—
U-0
—
SSPIE
SSPIF
RBIE
Bit 3
PSA
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
CCP1IE
CCP1IF
Note:
Bit 2
T0IF
PS2
—
—
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
TMR2IE
TMR2IF
INTF
Bit 1
PS1
—
—
U-0
—
software
TMR1IE
CCP2IE
TMR1IF
CCP2IF
Bit 0
RBIF
© 2009 Microchip Technology Inc.
PS0
x = Bit is unknown
U-0
should
—
0000 000x
1111 1111
0000 0000
---- ---0
0000 0000
---- ---0
POR, BOR
Value on
ensure
CCP2IF
0000 000x
1111 1111
0000 0000
---- ---0
0000 0000
---- ---0
R/W-0
Value on
all other
Resets
bit 0
the
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