PIC16F723A-E/MV Microchip Technology, PIC16F723A-E/MV Datasheet - Page 175
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC16F723A-E/MV
Manufacturer Part Number
PIC16F723A-E/MV
Description
7 KB Flash, 1.8V-5.5V, 16 MHz Int. Osc. 28 UQFN 4x4x0.5mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16F722AT-ISS.pdf
(284 pages)
Specifications of PIC16F723A-E/MV
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-UFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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REGISTER 17-4:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-0
SMP
SMP: SPI Data Input Sample Phase bit
1 = Slew Rate Control (limiting) disabled. Operating in I
0 = Slew Rate Control (limiting) enabled. Operating in I
CKE: SPI Clock Edge Select bit
This bit must be maintained clear. Used in SPI mode only.
D/A: DATA/ADDRESS bit (I
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit
This bit is cleared when the SSP module is disabled, or when the Start bit is detected last.
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
S: Start bit
This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last.
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
R/W: READ/WRITE bit Information
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or ACK bit.
1 = Read
0 = Write
UA: Update Address bit (10-bit I
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
Receive:
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit:
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
R/W-0
CKE
SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (I
W = Writable bit
‘1’ = Bit is set
R-0
D/A
2
C mode only)
2
C mode only)
R-0
P
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC16F/LF722A/723A
R-0
S
2
2
C Fast mode (400 kHz).
C Standard mode (100 kHz and 1 MHz).
R/W
R-0
x = Bit is unknown
R-0
UA
DS41417A-page 175
2
C MODE)
R-0
BF
bit 0
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