PIC16F723A-E/SP Microchip Technology, PIC16F723A-E/SP Datasheet - Page 176

• Manufacturer Part Number: PIC16F723A-E/SP
• Description: 7 KB Flash, 1.8V-5.5V, 16 MHz Int. Osc. 28 SPDIP .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F723A-E/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF722A/723A
REGISTER 17-5:
REGISTER 17-6:
TABLE 17-7:
DS41417A-page 176
INTCON
PIR1
PIE1
SSPBUF
SSPADD
SSPCON
SSPMSK
SSPSTAT
TRISC
Legend:
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-1
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Name
R/W-1
R/W-0
MSK7
ADD7
2:
(2)
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by SSP module in I
mode.
Maintain these bits clear in I
Accessible only when SSPM<3:0> = 1001.
Synchronous Serial Port Receive Buffer/Transmit Register
Synchronous Serial Port (I
Synchronous Serial Port (I
TMR1GIE
TMR1GIF
TRISC7
SMP
WCOL
MSK<7:1>: Mask bits
1 = The received address bit n is compared to SSPADD<n> to detect I
0 = The received address bit n is not used to detect I
MSK<0>: Mask bit for I
I
1 = The received address bit ‘0’ is compared to SSPADD<0> to detect I
0 = The received address bit ‘0’ is not used to detect I
All other SSP modes: this bit has no effect.
ADD<7:0>: Address bits
Received address
Bit 7
GIE
2
REGISTERS ASSOCIATED WITH I
C Slave Mode, 10-bit Address (SSPM<3:0> = 0111):
(1)
R/W-1
MSK6
R/W-0
ADD6
SSPMSK: SSP MASK REGISTER
SSPADD: SSP I
SSPOV
TRISC6
CKE
PEIE
ADIF
ADIE
Bit 6
(1)
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
R/W-1
MSK5
R/W-0
ADD5
TRISC5
SSPEN
2
RCIF
RCIE
2
2
Bit 5
T0IE
C mode.
D/A
C mode) Address Register
C mode) Address Mask Register
2
C Slave Mode, 10-bit Address
2
C ADDRESS REGISTER
TRISC4 TRISC3
Bit 4
INTE
TXIF
TXIE
CKP
P
R/W-1
R/W-0
MSK4
ADD4
SSPM3
SSPIF
SSPIE
RBIE
Bit 3
S
2
C OPERATION
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-1
MSK3
R/W-0
ADD3
CCP1IE
CCP1IF
TRISC2
SSPM2
Bit 2
T0IF
R/W
2
C address match
2
C address match
TMR2IE
TMR2IF
TRISC1
SSPM1
Bit 1
INTF
UA
R/W-1
R/W-0
MSK2
ADD2
TMR1IF
TMR1IE
TRISC0
SSPM0
RBIF
Bit 0
BF
 2010 Microchip Technology Inc.
2
C address match
2
x = Bit is unknown
C address match
x = Bit is unknown
0000 000x
0000 0000
0000 0000
xxxx xxxx
0000 0000
0000 0000
1111 1111
0000 0000
1111 1111
R/W-1
MSK1
R/W-0
ADD1
POR, BOR
Value on
0000 000u
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
1111 1111
0000 0000
1111 1111
R/W-1
Value on
MSK0
R/W-0
ADD0
all other
Resets
bit 0
bit 0
2
C