PIC16F872T-I/SO Microchip Technology, PIC16F872T-I/SO Datasheet - Page 64
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PIC16F872T-I/SO
Manufacturer Part Number
PIC16F872T-I/SO
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F872-ISO.pdf
(168 pages)
5.PIC16F872-ISO.pdf
(5 pages)
6.PIC16F872-ISO.pdf
(6 pages)
Specifications of PIC16F872T-I/SO
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16F872-ISO PDF datasheet #4
- PIC16F872-ISO PDF datasheet #5
- PIC16F872-ISO PDF datasheet #6
- Current page: 64 of 168
- Download datasheet (3Mb)
PIC16F872
9.2.3
While in SLEEP mode, the I
addresses or data. When an address match or com-
plete byte transfer occurs, wake the processor from
SLEEP (if the SSP interrupt is enabled).
TABLE 9-3:
DS30221C-page 62
0Bh, 8Bh,
10Bh,18Bh
0Ch
8Ch
0Dh
8Dh
13h
14h
91h
94h
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in I
Note 1: These bits are reserved; always maintain these bits clear.
Address
INTCON
PIR1
PIE1
PIR2
PIE2
SSPBUF
SSPCON
SSPCON2
SSPSTAT
SLEEP OPERATION
Name
REGISTERS ASSOCIATED WITH I
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
GCEN
Bit 7
SMP
GIE
(1)
(1)
—
—
2
C module can receive
ACKSTAT ACKDT ACKEN RCEN
SSPOV
PEIE
ADIF
ADIE
Bit 6
CKE
(1)
(1)
TMR0IE
SSPEN
Bit 5
D/A
(1)
(1)
—
—
INTE
EEIF
EEIE
Bit 4
CKP
(1)
(1)
P
2
C OPERATION
SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE r0rr 0000 0000 0000
BCLIE
BCLIF
RBIE
Bit 3
S
9.2.4
A RESET disables the SSP module and terminates the
current transfer.
TMR0IF
Bit 2
PEN
R/W
—
—
EFFECTS OF A RESET
RSEN
Bit 1
INTF
UA
(1)
(1)
CCP2IF -r-0 0--0 -r-0 0--0
CCP2IE -r-0 0--r -r-0 0--r
© 2006 Microchip Technology Inc.
Bit 0
RBIF
SEN
BF
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
Value on:
POR,
BOR
2
C mode.
Value on
RESETS
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