PIC16LF1507-E/P Microchip Technology, PIC16LF1507-E/P Datasheet - Page 56
![3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 PDIP .300in TUBE](/photos/16/12/161290/pdip20_sml.jpg)
PIC16LF1507-E/P
Manufacturer Part Number
PIC16LF1507-E/P
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 PDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC16F1507-EML.pdf
(266 pages)
Specifications of PIC16LF1507-E/P
Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Package / Case
PDIP-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
Details
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6.3
The Low-Power Brown-Out Reset (LPBOR) is an
essential part of the Reset subsystem. Refer to
Figure 6-1
modules.
The LPBOR is used to monitor the external V
When too low of a voltage is detected, the device is
held in Reset. When this occurs, a register bit (BOR) is
changed to indicate that a BOR Reset has occurred.
The same bit is set for both the BOR and the LPBOR.
Refer to
6.3.1
The LPBOR is controlled by the LPBOR bit of
Configuration Words. When the device is erased, the
LPBOR module defaults to disabled.
6.3.1.1
The output of the LPBOR module is a signal indicating
whether or not a Reset is to be asserted. This signal is
OR’d together with the Reset signal of the BOR mod-
ule to provide the generic BOR signal which goes to
the PCON register and to the power control block.
6.4
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE bit of Configuration Words and the LVP bit of
Configuration Words
TABLE 6-2:
6.4.1
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
V
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
6.4.2
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control. See Section 11.2 “PORTA Regis-
ters” for more information.
2011 Microchip Technology Inc.
DD
Note:
through an internal weak pull-up.
MCLRE
0
1
x
Register
Low-Power Brown-out Reset
(LPBOR)
MCLR
to see how the BOR interacts with other
ENABLING LPBOR
MCLR ENABLED
A Reset does not drive the MCLR pin low.
MCLR DISABLED
LPBOR Module Output
6-2.
MCLR CONFIGURATION
(Table
LVP
0
0
1
6-2).
Disabled
Enabled
Enabled
MCLR
DD
pin.
Preliminary
6.5
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 9.0
“Watchdog Timer” for more information.
6.6
A RESET instruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See
for default conditions after a RESET instruction has
occurred.
6.7
The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration
Words.
Reset” for more information.
6.8
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
6.9
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow V
running.
The Power-up Timer is controlled by the PWRTE bit of
Configuration Words.
6.10
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1.
2.
The total time-out will vary based on oscillator configu-
ration and Power-up
Section 5.0 “Oscillator Module” for more informa-
tion.
The Power-up Timer runs independently of MCLR
Reset. If MCLR is kept low long enough, the Power-up
Timer will expire. Upon bringing MCLR high, the device
will begin execution immediately (see
is useful for testing purposes or to synchronize more
than one device operating in parallel.
Power-up Timer runs to completion (if enabled).
MCLR must be released (if enabled).
DD
Watchdog Timer (WDT) Reset
RESET Instruction
Stack Overflow/Underflow Reset
Programming Mode Exit
Power-Up Timer
Start-up Sequence
See
to stabilize before allowing the device to start
PIC16(L)F1507
Section 3.4.2
Timer
“Overflow/Underflow
configuration.
DS41586A-page 56
Figure
6-3). This
Table 6-4
See
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