PIC16LF1826-E/SS Microchip Technology, PIC16LF1826-E/SS Datasheet - Page 95

• Manufacturer Part Number: PIC16LF1826-E/SS
• Description: 18 Pin, 3.5 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1826-E/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Processor Series: PIC16LF
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.5.5
The PIE4 register contains the interrupt enable bits, as
shown in Register 8-5.
REGISTER 8-5:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-2
bit 1
bit 0
Note 1:
U-0
—
This register is only available on PIC16F/LF1827.
PIE4 REGISTER
Unimplemented: Read as ‘0’
BCL2IE: MSSP2 Bus Collision Interrupt Enable bit
1 = Enables the MSSP2 Bus Collision Interrupt
0 = Disables the MSSP2 Bus Collision Interrupt
SSP2IE: Master Synchronous Serial Port 2 (MSSP2) Interrupt Enable bit
1 = Enables the MSSP2 interrupt
0 = Disables the MSSP2 interrupt
U-0
—
PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4
(1)
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U-0
—
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
U-0
—
Note 1: The PIE4 register is available only on the
PIC16F/LF1826/27
2: Bit PEIE of the INTCON register must be
PIC16F/LF1827 device.
set to enable any peripheral interrupt.
U-0
—
(1)
R/W-0/0
BCL2IE
DS41391C-page 95
R/W-0/0
SSP2IE
bit 0