PIC16LF1828-E/ML Microchip Technology, PIC16LF1828-E/ML Datasheet - Page 276

• Manufacturer Part Number: PIC16LF1828-E/ML
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core, Nan
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1828-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16(L)F1824/1828
25.6.2 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
releases the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate Gen-
erator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam-
pled high, the Baud Rate Generator is reloaded with
the contents of SSP1ADD<7:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count in the event that the clock
is held low by an external device
FIGURE 25-25:
25.6.3 WCOL STATUS FLAG
If the user writes the SSP1BUF when a Start, Restart,
Stop, Receive or Transmit sequence is in progress, the
WCOL is set and the contents of the buffer are
unchanged (the write doesn’t occur). Any time the
WCOL bit is set it indicates that an action on SSP1BUF
was attempted while the module was not Idle.
DS41419B-page 276
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSP1CON2 is disabled until the Start
condition is complete.
SDA
SCL
BRG
Value
BRG
Reload
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
03h
(Figure
DX
SCL deasserted but slave holds
SCL low (clock arbitration)
02h
25-25).
SCL is sampled high, reload takes
place and BRG starts its count
01h
Preliminary
BRG decrements on
Q2 and Q4 cycles
00h (hold off)
DX ‚
–
1
SCL allowed to transition high
03h
 2010 Microchip Technology Inc.
02h