PIC16LF1904-E/PT Microchip Technology, PIC16LF1904-E/PT Datasheet - Page 140

• Manufacturer Part Number: PIC16LF1904-E/PT
• Description: 7KB Flash, 256B RAM, LCD, 14x10b ADC, EUSART, NanoWatt XLP 44 TQFP 10x10x1mm TRA
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1904-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: LIN, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16LF1904/6/7
16.1.3
A software programmable prescaler is available for
exclusive use with Timer0. The prescaler is enabled by
clearing the PSA bit of the OPTION_REG register.
There are 8 prescaler options for the Timer0 module
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION_REG
register. In order to have a 1:1 prescaler value for the
Timer0 module, the prescaler must be disabled by set-
ting the PSA bit of the OPTION_REG register.
The prescaler is not readable or writable. All instructions
writing to the TMR0 register will clear the prescaler.
16.1.4
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The Timer0
interrupt enable is the TMR0IE bit of the INTCON
register.
16.1.5
When in 8-Bit Counter mode, the incrementing edge on
the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in
Specifications”.
16.1.6
Timer0 cannot operate while the processor is in Sleep
mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.
DS41569A-page 140
Note:
Note:
SOFTWARE PROGRAMMABLE
PRESCALER
The Watchdog Timer (WDT) uses its own
independent prescaler.
TIMER0 INTERRUPT
The Timer0 interrupt cannot wake the pro-
cessor from Sleep since the timer is fro-
zen during Sleep.
8-BIT COUNTER MODE
SYNCHRONIZATION
OPERATION DURING SLEEP
Section 22.0 “Electrical
Preliminary
 2011 Microchip Technology Inc.