PIC16LF1906T-I/SO Microchip Technology, PIC16LF1906T-I/SO Datasheet - Page 99
![14KB Flash, 512B RAM, LCD, 11x10b ADC, EUSART, NanoWatt XLP 28 SOIC .300in T/R](/photos/16/12/161267/qfn-28_sml.jpg)
PIC16LF1906T-I/SO
Manufacturer Part Number
PIC16LF1906T-I/SO
Description
14KB Flash, 512B RAM, LCD, 11x10b ADC, EUSART, NanoWatt XLP 28 SOIC .300in T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16LF1904-EMV.pdf
(288 pages)
Specifications of PIC16LF1906T-I/SO
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Program Memory Type
Flash
Data Ram Size
512 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
25
Number Of Timers
1 x 16-bit, 1 x 8-bit
Operating Supply Voltage
1.8 V to 5.5 V
Mounting Style
SMD/SMT
Package / Case
QFN-28
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
LIN, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
14KB (8K x 14)
Eeprom Size
-
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
Details
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REGISTER 10-5:
2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
S = Bit can only be set
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
U-1
—
2:
3:
(1)
Unimplemented bit, read as ‘ 1 ’.
The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1 ) .
The LWLO bit is ignored during a program memory erase operation (FREE = 1 ).
Unimplemented: Read as ‘ 1 ’
CFGS: Configuration Select bit
1 = Access Configuration, User ID and Device ID registers
0 = Access Flash program memory
LWLO: Load Write Latches Only bit
1 = Only the addressed program memory write latch is loaded/updated on the next WR command
0 = The addressed program memory write latch is loaded/updated and a write of all program memory write latches
FREE: Program Flash Erase Enable bit
1 = Performs an erase operation on the next WR command (hardware cleared upon completion)
0 = Performs a write operation on the next WR command
WRERR: Program/Erase Error Flag bit
1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically
0 = The program or erase operation completed normally.
WREN: Program/Erase Enable bit
1 = Allows program/erase cycles
0 = Inhibits programming/erasing of program Flash
WR: Write Control bit
1 = Initiates a program Flash program/erase operation.
0 = Program/erase operation to the Flash is complete and inactive.
RD: Read Control bit
1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set
0 = Does not initiate a program Flash read.
R/W-0/0
CFGS
will be initiated on the next WR command
on any set attempt (write ‘ 1 ’) of the WR bit).
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
(not cleared) in software.
PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
LWLO
R/W/HC-0/0
(3)
FREE
Preliminary
R/W/HC-x/q
U = Unimplemented bit, read as ‘0’
HC = Bit is cleared by hardware
-n/n = Value at POR and BOR/Value at all other Resets
WRERR
(2)
PIC16LF1904/6/7
R/W-0/0
WREN
R/S/HC-0/0
WR
DS41569A-page 99
R/S/HC-0/0
RD
bit 0
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