PIC16LF1936-E/SO Microchip Technology, PIC16LF1936-E/SO Datasheet - Page 18
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PIC16LF1936-E/SO
Manufacturer Part Number
PIC16LF1936-E/SO
Description
14KB Flash, 512B RAM, 256B EEPROM, LCD, NanoWatt XLP 28 SOIC .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Specifications of PIC16LF1936-E/SO
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC16F193X/LF193X/PIC16F194X/LF194X/
4.0
In Program/Verify mode, the program memory and the
configuration
programmed
ICSPCLK are used for the data and the clock,
respectively. All commands and data words are
transmitted LSb first. Data changes on the rising edge
of the ICSPCLK and latched on the falling edge. In
Program/Verify
ICSPCLK are Schmitt Trigger inputs. The sequence
that enters the device into Program/Verify mode
places all other logic into the Reset state. Upon
entering
automatically configured as high-impedance inputs
and the address is cleared.
4.1
There are two different methods of entering Program/
Verify mode via high-voltage:
• V
• V
4.1.1
To enter Program/Verify mode via the V
the following sequence must be followed:
1.
2.
3.
The V
code prior to entering Program/Verify mode. For
example, when the Configuration Word has MCLR
disabled (MCLRE = 0), the power-up time is disabled
(PWRTE = 0), the internal oscillator is selected
(F
application, the device will execute code. Since this
may prevent entry, V
recommended. See the timing diagram in
4.1.2
To enter Program/Verify mode via the V
the following sequence must be followed:
1.
2.
3.
The V
device when V
necessary to disconnect V
mode. See the timing diagram in
DS41397B-page 18
OSC
PP
DD
Hold ICSPCLK and ICSPDAT low. All other pins
should be unpowered.
Raise the voltage on MCLR from 0V to V
Raise the voltage on V
operating voltage.
Hold ICSPCLK and ICSPDAT low.
Raise the voltage on V
operating voltage.
Raise the voltage on MCLR from V
to V
PP
DD
= 100), and RB6 and RB7 are driven by the user
– First entry mode
– First entry mode
-first entry prevents the device from executing
IHH
-first method is useful when programming the
PROGRAM/VERIFY MODE
High-Voltage Program/Verify Mode
Entry and Exit
Program/Verify
.
V
V
PP
DD
in
memory
DD
– FIRST ENTRY MODE
– FIRST ENTRY MODE
mode
serial
is already applied, for it is not
PP
-first entry mode is strongly
both
can
DD
DD
DD
fashion.
mode,
from 0V to the desired
from 0V to the desired
to enter Program/Verify
the
be
Figure
accessed
ICSPDAT
ICSPDAT
all
DD
PP
DD
8-2.
-first method
-first method
Figure
or below
I/O’s
IHH
.
8-3.
and
and
and
are
4.1.3
To exit Program/Verify mode take MCLR to V
lower (V
4.2
The Low-Voltage Programming mode allows the
PIC16F193X/LF193X/PIC16F194X/LF194X/
PIC16LF190X devices to be programmed using V
only, without high voltage. When the LVP bit of the
Configuration Word 2 register is set to ‘1’, the low-
voltage ICSP programming entry is enabled. To disable
the Low-Voltage ICSP mode, the LVP bit must be
programmed to ‘0’. This can only be done while in the
High-Voltage Entry mode.
Entry into the Low-Voltage ICSP Program/Verify modes
requires the following steps:
1.
2.
The key sequence is a specific 32-bit pattern, '0100
1101 0100 0011 0100 1000 0101 0000' (more
easily remembered as MCHP in ASCII). The device will
enter Program/Verify mode only if the sequence is
valid. The Least Significant bit of the Least Significant
nibble must be shifted in first.
Once the key sequence is complete, MCLR must be
held at V
maintained.
For low-voltage programming timing, see Figures
and 8-10.
Exiting Program/Verify mode is done by no longer
driving MCLR to V
Note:
MCLR is brought to V
A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
IL
IL
Low-Voltage Programming (LVP)
Mode
). See Figures
for as long as Program/Verify mode is to be
PROGRAM/VERIFY MODE EXIT
To enter LVP mode, the LSB of the Least
Significant nibble must be shifted in first.
This differs from entering the key
sequence on other parts.
IL
. See Figures
2010 Microchip Technology Inc.
8-4
IL
.
and 8-5.
8-9
and 8-10.
DD
8-9
DD
or