PIC16LF1936-E/SP Microchip Technology, PIC16LF1936-E/SP Datasheet - Page 51
PIC16LF1936-E/SP
Manufacturer Part Number
PIC16LF1936-E/SP
Description
14KB Flash, 512B RAM, 256B EEPROM, LCD, NanoWatt XLP 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Specifications of PIC16LF1936-E/SP
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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TABLE 3-14:
2009 Microchip Technology Inc.
780h
781h
782h
783h
784h
785h
786h
787h
788h
789h
78Ah
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
79Fh
7A0h
7A1h
7A2h
7A3h
7A4h
7A5h
Legend:
Note
Address
Bank 15
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1, 2)
(2)
1:
2:
3:
4:
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
LCDCON
LCDPS
LCDREF
LCDCST
LCDRL
—
—
LCDSE0
LCDSE1
LCDSE2
—
—
—
—
—
LCDDATA0
LCDDATA1
LCDDATA2
LCDDATA3
LCDDATA4
LCDDATA5
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are trans-
ferred to the upper byte of the program counter.
These registers can be addressed from any bank.
These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
The Capacitive Sensing Reference Mode (CPSRM) bit is not available for the PIC16F/LF1934/1936/1937 devices.
Name
(3)
(3)
(3)
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
Working Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
LCDIRE
LCDEN
SEG15
SEG23
SEG15
SEG23
COM0
COM0
COM0
COM1
COM1
COM1
SEG7
SEG7
Bit 7
WFT
GIE
—
—
—
—
LRLAP
Write Buffer for the upper 7 bits of the Program Counter
<1:0>
BIASMD
LCDIRS
SLPEN
SEG14
SEG22
SEG14
SEG22
COM0
COM0
COM0
COM1
COM1
COM1
SEG6
SEG6
PEIE
Bit 6
—
—
—
TMR0IE
LCDIRI
SEG13
SEG21
SEG13
SEG21
WERR
COM0
COM0
COM0
COM1
COM1
COM1
LCDA
SEG5
SEG5
Bit 5
—
—
—
LRLBP
Preliminary
<1:0>
SEG12
SEG20
SEG12
SEG20
COM0
COM0
COM0
COM1
COM1
COM1
SEG4
SEG4
Bit 4
INTE
WA
TO
—
—
—
SE<23:16>
SE<15:8>
SE<7:0>
VLCD3PE
SEG11
SEG19
SEG11
SEG19
COM0
COM0
COM0
COM1
COM1
COM1
IOCIE
SEG3
SEG3
PIC16F193X/LF193X
Bit 3
PD
—
—
CS
<1:0>
BSR<4:0>
VLCD2PE VLCD1PE
TMR0IF
SEG10
SEG18
SEG10
SEG18
COM0
COM0
COM0
COM1
COM1
COM1
SEG2
SEG2
Bit 2
Z
LP
<3:0>
LCDCST
LRLAT
SEG17
SEG17
COM0
COM0
COM0
COM1
COM1
COM1
SEG1
SEG9
SEG1
SEG9
INTF
Bit 1
DC
LMUX
<2:0>
<2:0>
<1:0>
SEG16
SEG16
COM0
COM0
COM0
COM1
COM1
COM1
IOCIF
SEG0
SEG8
SEG0
SEG8
Bit 0
—
C
DS41364D-page 51
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
000- 0011 000- 0011
0000 0000 0000 0000
000- 000- 000- 000-
---- -000 ---- -000
0000 -000 0000 -000
0000 0000 uuuu uuuu
0000 0000 uuuu uuuu
0000 0000 uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
POR, BOR
Value on:
—
—
—
—
—
—
—
—
—
—
—
—
Value on all
Resets
other
—
—
—
—
—
—
—
—
—
—
—
—
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