PIC16LF723A-E/MV Microchip Technology, PIC16LF723A-E/MV Datasheet - Page 189
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PIC16LF723A-E/MV
Manufacturer Part Number
PIC16LF723A-E/MV
Description
7 KB Flash, 16 MHz Int. Osc, NanoWatt XLP 28 UQFN 4x4x0.5mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16F722AT-ISS.pdf
(284 pages)
Specifications of PIC16LF723A-E/MV
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-UFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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DECFSZ
Syntax:
Operands:
Operation:
Status Affected:
Description:
GOTO
Syntax:
Operands:
Operation:
Status Affected:
Description:
INCF
Syntax:
Operands:
Operation:
Status Affected:
Description:
2010 Microchip Technology Inc.
Decrement f, Skip if 0
[ label ] DECFSZ f,d
0 f 127
d [0,1]
(f) - 1 (destination);
skip if result = 0
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘0’, then a NOP is
executed instead, making it a
2-cycle instruction.
Unconditional Branch
[ label ]
0 k 2047
k PC<10:0>
PCLATH<4:3> PC<12:11>
None
GOTO is an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a
two-cycle instruction.
Increment f
[ label ]
0 f 127
d [0,1]
(f) + 1 (destination)
Z
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
GOTO k
INCF f,d
PIC16F/LF722A/723A
INCFSZ
Syntax:
Operands:
Operation:
Status Affected:
Description:
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Increment f, Skip if 0
[ label ]
0 f 127
d [0,1]
(f) + 1 (destination),
None
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘0’, a NOP is executed
instead, making it a 2-cycle
instruction.
Inclusive OR W with f
[ label ]
0 f 127
d [0,1]
(W) .OR. (f) (destination)
Z
Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
skip if result = 0
Inclusive OR literal with W
[ label ]
0 k 255
(W) .OR. k (W)
Z
The contents of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the
W register.
INCFSZ f,d
IORWF
IORLW k
DS41417A-page 189
f,d
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