PIC16LF727-E/MV Microchip Technology, PIC16LF727-E/MV Datasheet - Page 174
![14 KB Flash, 16 MHz Int. Osc, NanoWatt XLP 40 UQFN 5x5x0.5mm TUBE](/photos/16/12/161286/qfn44_sml.jpg)
PIC16LF727-E/MV
Manufacturer Part Number
PIC16LF727-E/MV
Description
14 KB Flash, 16 MHz Int. Osc, NanoWatt XLP 40 UQFN 5x5x0.5mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.AC164112.pdf
(302 pages)
Specifications of PIC16LF727-E/MV
Processor Series
PIC16F
Core
PIC
Program Memory Type
Flash
Program Memory Size
7 KB
Data Ram Size
192 B
Interface Type
I2C, SPI, AUSART
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
UQFN-44
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
-
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
Details
- Current page: 174 of 302
- Download datasheet (5Mb)
PIC16F72X/PIC16LF72X
REGISTER 17-1:
DS41341E-page 174
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
WCOL
R/W-0
When enabled, these pins must be properly configured as input or output.
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
0 = No collision
SSPOV: Receive Overflow Indicator bit
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCK, SDO and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = F
0001 = SPI Master mode, clock = F
0010 = SPI Master mode, clock = F
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
SSPOV
R/W-0
software)
overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read
the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the over-
flow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPBUF register.
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (SPI MODE)
W = Writable bit
‘1’ = Bit is set
SSPEN
R/W-0
R/W-0
CKP
OSC
OSC
OSC
/4
/16
/64
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPM3
R/W-0
SSPM2
R/W-0
© 2009 Microchip Technology Inc.
x = Bit is unknown
SSPM1
R/W-0
(1)
SSPM0
R/W-0
bit 0
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