PIC18F25K22-E/SP Microchip Technology, PIC18F25K22-E/SP Datasheet - Page 51
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PIC18F25K22-E/SP
Manufacturer Part Number
PIC18F25K22-E/SP
Description
32KB, Flash, 1536bytes-RAM,8-bit Family 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F25K22T-ISS.pdf
(10 pages)
Specifications of PIC18F25K22-E/SP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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3.3
The Power-Managed Sleep mode in the PIC18(L)F2X/
4XK22 devices is identical to the legacy Sleep mode
offered in all other PIC
entered by clearing the IDLEN bit of the OSCCON
register and executing the SLEEP instruction. This shuts
down the selected oscillator
source status bits are cleared.
Entering the Sleep mode from either Run or Idle mode
does not require a clock switch. This is because no
clocks are needed once the controller has entered
Sleep. If the WDT is selected, the LFINTOSC source
will continue to operate. If the SOSC oscillator is
enabled, it will also continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS<1:0> bits
becomes ready (see
from the internal oscillator block if either the Two-Speed
Start-up or the Fail-Safe Clock Monitor are enabled
(see
either case, the OSTS bit is set when the primary clock
is providing the device clocks. The IDLEN and SCS bits
are not affected by the wake-up.
FIGURE 3-4:
2010 Microchip Technology Inc.
Peripheral
Program
Counter
Section 24.0 “Special Features of the
OSC1
Clock
Clock
Sleep
CPU
Sleep Mode
Q1
Q2
PC
Q3
Figure
Q4
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
®
microcontroller devices. It is
Q1
3-5), or it will be clocked
(Figure
3-4) and all clock
CPU”). In
Preliminary
PC + 2
3.4
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected by the SCS<1:0> bits; however, the CPU
will not be clocked. The clock source status bits are not
affected. Setting IDLEN and executing a SLEEP instruc-
tion provides a quick method of switching from a given
Run mode to its corresponding Idle mode.
If the WDT is selected, the LFINTOSC source will con-
tinue to operate. If the SOSC oscillator is enabled, it will
also continue to run.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out, or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of T
becomes ready to execute code. When the CPU
begins executing code, it resumes with the same clock
source for the current Idle mode. For example, when
waking from RC_IDLE mode, the internal oscillator
block will clock the CPU and peripherals (in other
words, RC_RUN mode). The IDLEN and SCS bits are
not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode
currently specified by the SCS<1:0> bits.
PIC18(L)F2X/4XK22
Idle Modes
DS41412D-page 51
CSD
while it
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