PIC18F25K80-E/SO Microchip Technology, PIC18F25K80-E/SO Datasheet - Page 111
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PIC18F25K80-E/SO
Manufacturer Part Number
PIC18F25K80-E/SO
Description
ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 SOIC .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F25K80-E/SO
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Processor Series
PIC18F25K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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6.2.3
The program memory is addressed in bytes. Instruc-
tions are stored as two or four bytes in program
memory. The Least Significant Byte (LSB) of an
instruction word is always stored in a program memory
location with an even address (LSB = 0 ). To maintain
alignment with instruction boundaries, the PC incre-
ments in steps of two and the LSB will always read ‘ 0 ’
(see
Figure 6-5
are stored in the program memory.
FIGURE 6-5:
6.2.4
The standard PIC18 instruction set has four, two-word
instructions: CALL , MOVFF , GOTO and LSFR . In all cases,
the second word of the instructions always has ‘ 1111 ’ as
its four Most Significant bits (MSbs). The other 12 bits
are literal data, usually a data memory address.
The use of ‘ 1111 ’ in the 4 MSbs of an instruction
specifies a special form of NOP . If the instruction is
executed in proper sequence, immediately after the
first word, the data in the second word is accessed and
EXAMPLE 6-4:
2011 Microchip Technology Inc.
CASE 1:
Object Code
CASE 2:
Object Code
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
Section 6.1.2 “Program Counter”
shows an example of how instruction words
INSTRUCTIONS IN PROGRAM
MEMORY
TWO-WORD INSTRUCTIONS
Instruction 1:
Instruction 2:
Instruction 3:
INSTRUCTIONS IN PROGRAM MEMORY
TWO-WORD INSTRUCTIONS
Program Memory
Byte Locations
MOVLW
GOTO
MOVFF
Source Code
TSTFSZ
Source Code
MOVFF
ADDWF
TSTFSZ
MOVFF
ADDWF
).
055h
0006h
123h, 456h
REG1
REG1, REG2 ; No, skip this word
REG3
REG1
REG1, REG2 ; Yes, execute this word
REG3
Preliminary
LSB = 1
; is RAM location 0?
; Execute this word as a NOP
; continue code
; is RAM location 0?
; 2nd word of instruction
; continue code
PIC18F66K80 FAMILY
EFh
C1h
0Fh
F0h
F4h
The CALL and GOTO instructions have the absolute
program memory address embedded into the instruc-
tion. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC<20:1>
which accesses the desired byte address in program
memory. Instruction #2 in
instruction, GOTO 0006h , is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. For more details on the instruction set, see
Section 29.0 “Instruction Set Summary”
used by the instruction sequence. If the first word is
skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC.
Note:
Example 6-4
LSB = 0
55h
03h
00h
23h
56h
For information on two-word instructions
in the extended instruction set, see
Section 6.5 “Program Memory and the
Extended Instruction Set”
shows how this works.
Word Address
00000Ah
00000Ch
00000Eh
000000h
000002h
000004h
000006h
000008h
000010h
000012h
000014h
Figure 6-5
DS39977C-page 111
shows how the
.
.
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