PIC18F25K80T-I/MM Microchip Technology, PIC18F25K80T-I/MM Datasheet - Page 272
![ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm T/R](/photos/16/12/161267/qfn-28_sml.jpg)
PIC18F25K80T-I/MM
Manufacturer Part Number
PIC18F25K80T-I/MM
Description
ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F25K80T-I/MM
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC18F25K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3648 B
Interface Type
I2C, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F25K80T-I/MM
Manufacturer:
MICROCHIP
Quantity:
3 000
- Current page: 272 of 628
- Download datasheet (6Mb)
PIC18F66K80 FAMILY
REGISTER 20-1:
DS39977C-page 272
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-4
bit 3-0
R/W-0
P1M1
P1M<1:0>: Enhanced PWM Output Configuration bits
If CCP1M<3:2> = 00 , 01 , 10 :
xx = P1A assigned as capture/compare input/output; P1B, P1C and P1D assigned as port pins
If CCP1M<3:2> = 11 :
00 = Single output: P1A, P1B, P1C and P1D controlled by steering (see
01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive
10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C and P1D assigned as
11 = Full-bridge output reverse: P1B modulated; P1C active; P1A and P1D inactive
DC1B<1:0> : PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found
in CCPR1L.
CCP1M<3:0> : ECCP1 Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCP1 module)
0001 = Reserved
0010 = Compare mode, toggle output on match
0011 = Capture mode
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every fourth rising edge
0111 = Capture mode, every 16
1000 = Compare mode, initialize ECCP1 pin low, set output on compare match (set CCP1IF)
1001 = Compare mode, initialize ECCP1 pin high, clear output on compare match (set CCP1IF)
1010 = Compare mode, generate software interrupt only, ECCP1 pin reverts to I/O state
1011 = Compare mode, trigger special event (ECCP1 resets TMR1 or TMR3, starts A/D conversion,
1100 = PWM mode; P1A and P1C active-high; P1B and P1D active-high
1101 = PWM mode; P1A and P1C active-high; P1B and P1D active-low
1110 = PWM mode; P1A and P1C active-low; P1B and P1D active-high
1111 = PWM mode; P1A and P1C active-low; P1B and P1D active-low
R/W-0
P1M0
Mode”
port pins
CCP1CON: ENHANCED CAPTURE/COMPARE/PWM1 CONTROL
sets CCP1IF bit)
)
W = Writable bit
‘1’ = Bit is set
DC1B1
R/W-0
DC1B0
R/W-0
th
Preliminary
rising edge
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CCP1M3
R/W-0
CCP1M2
R/W-0
Section 20.4.7 “Pulse Steering
2011 Microchip Technology Inc.
x = Bit is unknown
CCP1M1
R/W-0
CCP1M0
R/W-0
bit 0
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