PIC18F27J53T-I/SS Microchip Technology, PIC18F27J53T-I/SS Datasheet - Page 5
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PIC18F27J53T-I/SS
Manufacturer Part Number
PIC18F27J53T-I/SS
Description
28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SSOP .20
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F27J53T-I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
7. Module: Enhanced Universal
EXAMPLE 1:
2010 Microchip Technology Inc.
;Initial conditions: SPEN = 0 (module disabled)
;To re-enable the module:
;Re-Initialize TXSTAx, BAUDCONx, SPBRGx, SPBRGHx registers (if needed)
;Re-Initialize RCSTAx register (if needed), but do not set SPEN = 1 yet
;Now enable the module, but add a 2-Tcy delay before executing any two-cycle
;instructions
bsf
nop
nop
In rare situations when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (SPEN bit
• The EUSART is re-enabled (RCSTAx<7> = 1)
• A two-cycle instruction is executed immediately
(RCSTAx<7>) = 0)
after setting SPEN, CREN or TXEN = 1
RCSTA1, SPEN
Synchronous Asynchronous
Receiver Transmitter (EUSART)
RE-ENABLING AN EUSART MODULE
;or RCSTA2 if EUSART2
;1 Tcy delay
;1 Tcy delay (two total)
PIC18F47J53 FAMILY
Work around
Add a 2 T
enables the EUSART module (sets SPEN, CREN
or TXEN = 1).
See
Affected Silicon Revisions
A1
X
Example
CY
delay after any instruction that re-
1.
DS80506C-page 5