PIC18F43K20-I/ML Microchip Technology, PIC18F43K20-I/ML Datasheet - Page 9
![8 KB Enh Flash, 768 RAM, 36 I/O, Nanowatt XLP 44 QFN 8x8x0.9mm TUBE](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F43K20-I/ML
Manufacturer Part Number
PIC18F43K20-I/ML
Description
8 KB Enh Flash, 768 RAM, 36 I/O, Nanowatt XLP 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(456 pages)
3.PIC18F23K20-ISS.pdf
(10 pages)
Specifications of PIC18F43K20-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
In addition to the code memory space, there are three
blocks in the configuration and ID space that are
accessible to the user through table reads and table
writes. Their locations in the memory map are shown in
Figure 2-10.
Users may store identification information (ID) in eight
ID registers. These ID registers are mapped in
addresses 200000h through 200007h. The ID locations
read out normally, even after code protection is applied.
Locations 300000h through 30000Dh are reserved for
the Configuration bits. These bits select various device
options and are described in Section 5.0 “Configura-
tion Word”. These Configuration bits read out
normally, even after code protection.
Locations 3FFFFEh and 3FFFFFh are reserved for the
device ID bits. These bits may be used by the program-
mer to identify what device type is being programmed
and are described in Section 5.0 “Configuration
Word”. These device ID bits read out normally, even
after code protection.
FIGURE 2-10:
© 2009 Microchip Technology Inc.
2FFFFFh
000000h
01FFFFh
1FFFFFh
3FFFFFh
Note:
Unimplemented
Sizes of memory areas are not to scale.
Code Memory
Configuration
CONFIGURATION AND ID LOCATIONS FOR PIC18F2XK20/4XK20 DEVICES
Read as ‘0’
and ID
Space
Advance Information
2.3.1
Memory in the address space, 0000000h to 3FFFFFh,
is addressed via the Table Pointer register, which is
comprised of three Pointer registers:
• TBLPTRU, at RAM address 0FF8h
• TBLPTRH, at RAM address 0FF7h
• TBLPTRL, at RAM address 0FF6h
The 4-bit command, ‘0000’ (core instruction), is used to
load the Table Pointer prior to using any read or write
operations.
PIC18F2XK20/4XK20
Addr[21:16]
TBLPTRU
MEMORY ADDRESS POINTER
ID Location 1
ID Location 2
ID Location 3
ID Location 4
ID Location 5
ID Location 6
ID Location 7
ID Location 8
CONFIG1H
CONFIG2H
CONFIG3H
CONFIG4H
CONFIG5H
CONFIG6H
CONFIG7H
CONFIG1L
CONFIG2L
CONFIG3L
CONFIG4L
CONFIG5L
CONFIG6L
CONFIG7L
Device ID1
Device ID2
TBLPTRH
Addr[15:8]
3FFFFEh
3FFFFFh
30000Ah
30000Bh
30000Ch
30000Dh
200000h
200001h
200002h
200003h
200004h
200005h
200006h
200007h
300000h
300001h
300002h
300003h
300004h
300005h
300006h
300007h
300008h
300009h
DS41297F-page 9
TBLPTRL
Addr[7:0]