PIC18F44K20-E/ML Microchip Technology, PIC18F44K20-E/ML Datasheet - Page 10

• Manufacturer Part Number: PIC18F44K20-E/ML
• Description: 16KB, Flash, 768bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 44 QFN 8x8x0.9mm TUB
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F44K20-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPDM164124 - KIT STARTER FOR PIC18F4XK20AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F24K20/25K20/44K20/45K20
34. Module: MSSP I
35. Module: EUSART
DS80425G-page 10
In Master I
occurs in the middle of an address or data
reception, then the SCL clock stream will continue
endlessly and the RCEN bit of the SSPCON2
register will remain set improperly. If a Start
condition occurs after the improper Stop condition
then 9 additional clocks will be generated followed
by the RCEN bit going low.
Work around
Use low-impedance pull-ups on the SDA line to
reduce the possibility of noise glitches which may
trigger an improper Stop event. Use a time-out
event timer to detect the unexpected Stop
condition and resulting stuck RCEN bit. Clear the
stuck RCEN bit by clearing the SSPEN bit of
SSPCON1.
Affected Silicon Revisions
The OERR flag of the RCSTA register is reset only
by clearing the CREN bit of the RCSTA register or
by a device Reset. Clearing the SPEN bit of the
RCSTA register does not clear the OERR flag.
Work around
Clear the OERR flag by clearing the CREN bit
instead of clearing the SPEN bit.
Affected Silicon Revisions
2
C Receive mode if a Stop condition
2
C™
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36. Module: EUSART
37. Module: Interrupt-on-Change
In Asynchronous Receive mode, the RCIDL bit of
the BAUDCON register will properly go low when
an invalid Start bit less than 1/16th of a bit time is
received. The RCIDL bit will then properly go high
1/8th of a bit time later. However, if another invalid
Start bit occurs less than 1 bit time after the leading
edge of the first invalid Start bit, then the RCIDL bit
will improperly stay high then improperly go low
one bit time later. The RCIDL bit will then stay low
improperly until a valid Start bit is received.
Work around
When monitoring the RCIDL bit, measure the
length of time between the RCIDL going low and
the RCIF flag going high. If this time is greater than
one character time, then restore the RCIDL bit by
resetting the EUSART module. The EUSART
module is reset when the SPEN bit of the RCSTA
register is cleared.
Affected Silicon Revisions
When any interrupt-on-change is enabled and the
corresponding input is high, then waking from
Sleep by a source other than interrupt-on-change
may cause the RBIF interrupt flag bit to become
set improperly.
Work around
Or
Affected Silicon Revisions
1. Use the INTx interrupt in lieu of interrupt-on-
2. Store the state of the PORTB inputs before
change.
entering Sleep. Upon waking, if an RBIF is
detected, then compare the PORTB levels
with those stored. If they are the same, then
clear and ignore the RBIF interrupt.
 2010 Microchip Technology Inc.
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