PIC18F65K90T-I/PT Microchip Technology, PIC18F65K90T-I/PT Datasheet - Page 209
PIC18F65K90T-I/PT
Manufacturer Part Number
PIC18F65K90T-I/PT
Description
32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F66K90-IMR.pdf
(570 pages)
Specifications of PIC18F65K90T-I/PT
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
32 KB
Data Ram Size
2 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
64 MHz
Number Of Timers
8
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F65K90T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Company:
Part Number:
PIC18F65K90T-I/PTRSL
Manufacturer:
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Quantity:
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FIGURE 15-5:
15.5.5
When Timer3/5/7 gate value status is utilized, it is
possible to read the most current level of the gate con-
trol value. The value is stored in the TxGVAL bit
(TxGCON<2>). The TxGVAL bit is valid even when the
Timer3/5/7 gate is not enabled (TMRxGE bit is
cleared).
2009-2011 Microchip Technology Inc.
Timer3/5/7
TMRxGIF
TMRxGE
TxGSPM
TxDONE
TxGPOL
TxGGO/
TxGVAL
TxG_IN
TxGTM
TxCKI
TIMER3/5/7 GATE VALUE STATUS
TIMER3/5/7 GATE SINGLE PULSE AND TOGGLE COMBINED MODE
Cleared by Software
N
Set by Software
Counting Enabled on
Rising Edge of TxG
N + 1
PIC18F87K90 FAMILY
Falling Edge of TxGVAL
N + 2
15.5.6
When the Timer3/5/7 gate event interrupt is enabled, it
is possible to generate an interrupt upon the comple-
tion of a gate event. When the falling edge of TxGVAL
occurs, the TMRxGIF flag bit in the PIRx register will be
set. If the TMRxGIE bit in the PIEx register is set, then
an interrupt will be recognized.
The TMRxGIF flag bit operates even when the Timer3/
5/7 gate is not enabled (TMRxGE bit is cleared).
Set by Hardware on
N + 3
TIMER3/5/7 GATE EVENT
INTERRUPT
N + 4
Cleared by Hardware on
Falling Edge of TxGVAL
DS39957D-page 209
Cleared by
Software
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