PIC18F67J93T-I/PT Microchip Technology, PIC18F67J93T-I/PT Datasheet - Page 3

• Manufacturer Part Number: PIC18F67J93T-I/PT
• Description: Segmented LCD, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F67J93T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3923 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Silicon Errata Issues
1. Module: MSSP (I
© 2009 Microchip Technology Inc.
Note:
In extremely rare cases when configured for I
slave reception, the MSSP module may not
receive the correct data. This occurs only if the
Serial Receive/Transmit Buffer register (SSPBUF)
is not read within a window after the SSPIF
interrupt (PIR1<3>) has occurred.
Work around
The issue can be resolved in either of these ways:
• Prior to the I
• Each time the SSPIF is set, read the SSPBUF
Affected Silicon Revisions
A1
clock stretching feature.
This
(SSPCON2<0>).
before the first rising clock edge of the next byte
being received.
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A1).
is
done
2
C slave reception, enable the
2
by
C™ Slave)
setting
the
SEN
2
C™
bit
PIC18F87J93 FAMILY
2. Module: Enhanced Universal
3. Module: Real-Time Clock and Calendar
1.
2.
3.
In rare situations when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (SPEN bit
• The EUSART is re-enabled (RCSTAx<7> = 1)
• A two-cycle instruction is executed
Work around
Add a 2 T
1. Disable
2. Disable the EUSART (RCSTAx<7> = 0).
3. Re-enable the EUSART (RCSTAx<7> = 1).
4. Re-enable receive interrupts (PIE1<5> = 1).
(This is the first T
5. Execute a NOP instruction.
(This is the second T
Affected Silicon Revisions
The INTRC is not automatically enabled as the
clock source for the RTCC module when the
INTRC clock is selected (CONFIG3L<1> = 0) and
the RTCC module is enabled (RTCCFG<7> = 1).
Work around
In order to enable the INTRC, at least one of the
following has to be enabled:
Watchdog
CONFIG1L<0>).
Two-Speed
CONFIG2L<7>).
Fail-Safe Clock Monitor Enable bit (FCMEN,
CONFIG2L<6>).
Affected Silicon Revisions
A1
A1
(RCSTAx<7>) = 0)
X
X
(PIE1<5>) = 0).
CY
Synchronous Asynchronous
Receiver Transmitter (EUSART)
(RTCC)
delay after re-enabling the EUSART.
Timer
receive
Start-up
CY
delay.)
CY
Enable
interrupts
delay.)
Enable
bit
DS80476A-page 3
(RCxIE
bit
(WDTEN,
(IESO,
bit