PIC18F87J72T-I/PT Microchip Technology, PIC18F87J72T-I/PT Datasheet
PIC18F87J72T-I/PT
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PIC18F87J72T-I/PT Summary of contents
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... Microcontrollers with Dual Channel AFE, LCD Driver and nanoWatt Technology 2010 Microchip Technology Inc. PIC18F87J72 Family Data Sheet 80-Pin, High-Performance Preliminary DS39979A ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Eight user-selectable frequencies from 31.25 kHz to 8 MHz • Secondary Oscillator using Timer1 at 32 kHz • Fail-Safe Clock Monitor (FSCM): - Allows for safe shutdown if peripheral clock fails 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Low-Power Features: • Power-Managed modes: - Run: CPU on, peripherals on ...
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... The CCP2 pin placement depends on the setting of the CCP2MX Configuration bit. DS39979A-page 4 A/D LCD I/O 132 132 PIC18F86J72 PIC18F87J72 Preliminary Y 1 1/1 1 1/1 1 SDOA 60 SCKA 59 CSA 58 RB0/INT0/SEG30 57 RB1/INT1/SEG8 56 RB2/INT2/SEG9/CTED1 55 RB3/INT3/SEG10/CTED2 54 RB4/KBI0/SEG11 53 RB5/KBI1/SEG29 52 RB6/KBI2/PGC OSC2/CLKO/RA6 49 OSC1/CLKI/RA7 RB7/KBI3/PGD 46 RC5/SDO/SEG12 45 RC4/SDI/SDA/SEG16 44 RC3/SCK/SCL/SEG17 43 RC2/CCP1/SEG13 42 CLKIA Dedicated 24-bit AFE pins 2010 Microchip Technology Inc. ...
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... Generic current sense configuration shown. Many circuit configurations using current and/or voltage sensing are possible, including the use of shunts, transformers or Rogowski coils. 2: Power metering, with the measurement of active and reactive power, is done with the power metering firmware application available through Microchip Technology. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 10 MHz ...
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... Packaging Information.............................................................................................................................................................. 429 Appendix A: Revision History............................................................................................................................................................. 433 Appendix B: Dual-Channel, 24-Bit AFE Reference............................................................................................................................ 434 The Microchip Web Site ..................................................................................................................................................................... 477 Customer Change Notification Service .............................................................................................................................................. 477 Customer Support .............................................................................................................................................................................. 477 Reader Response .............................................................................................................................................................................. 478 Product Identification System............................................................................................................................................................. 479 DS39979A-page 6 Preliminary 2010 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Preliminary DS39979A-page 7 ...
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... PIC18F87J72 FAMILY NOTES: DS39979A-page 8 Preliminary 2010 Microchip Technology Inc. ...
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... MHz, for a total of eight clock frequencies. This option frees the two oscillator pins for use as additional general purpose I/O. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY The internal oscillator block provides a stable reference source that gives the family additional features for robust operation: • ...
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... CPU. The module is a 100-year clock and calendar with automatic leap year detection. The range of the clock is from 00:00:00 (midnight) on January 1, 2000 to 23:59:59 on December 31, 2099. Preliminary 2010 Microchip Technology Inc. 2 C™ (Master and ...
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... Analog-to-Digital Module Dual-Channel 24-Bit Analog Front End Resets (and Delays) Instruction Set Packages 2010 Microchip Technology Inc. PIC18F87J72 FAMILY The devices are differentiated in that PIC18F86J72 devices have a Flash program memory of 64 Kbytes and PIC18F87J72 devices memory is 128 Kbytes All other features for the devices are identical. These are summarized in Table 1-1 ...
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... MSSP Preliminary PORTA (1,2) RA0:RA7 PORTB (1) RB0:RB7 4 PORTC (1) RC0:RC7 12 PORTD (1) RD0:RD7 PORTE RE0:RE1, 8 (1) RE3:RE7 PORTF 8 (1) RF1:RF7 8 8 PORTG (1) RG0:RG4 SDIA CHn+ SDOA CLKIA CHn- CSA DR Comparators Dual-Channel AFE LCD SV SAV ARESET SAV Driver SS SS 2010 Microchip Technology Inc. ...
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... I = Input P = Power Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Pin Buffer Type Type I ST Master Clear (input) or programming voltage (input). This pin is an active-low Reset to the device ...
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... In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output Analog = Analog input OD = Open-Drain (no P diode Output Preliminary Description ) DD 2010 Microchip Technology Inc. ...
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... C/SMBus compatible input I = Input P = Power Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O ...
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... Digital I/O. O Analog SEG5 output for LCD. I/O ST Digital I/O. O Analog SEG6 output for LCD. I/O ST Digital I/O. O Analog SEG7 output for LCD. CMOS = CMOS compatible input or output Analog = Analog input OD = Open-Drain (no P diode Output Preliminary Description ) DD 2010 Microchip Technology Inc. ...
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... C/SMBus compatible input I = Input P = Power Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port. I/O ST Digital I/O ...
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... SEG24 output for LCD I Analog Comparator 1 Input A. I/O ST Digital I/O. O Analog Analog Input 5. I TTL SPI slave select input. O Analog SEG25 output for LCD. CMOS = CMOS compatible input or output Analog = Analog input OD = Open-Drain (no P diode Output Preliminary Description ) DD 2010 Microchip Technology Inc. ...
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... C/SMBus compatible input I = Input P = Power Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Pin Buffer Type Type PORTG is a bidirectional I/O port. I/O ST Digital I/O ...
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... AFE serial interface chip select pin. I TTL AFE serial interface clock pin. O TTL AFE serial interface data output pin. I TTL AFE serial interface data input pin. CMOS = CMOS compatible input or output Analog = Analog input OD = Open-Drain (no P diode Output Preliminary Description ) DD 2010 Microchip Technology Inc. ...
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... REF reference for analog modules is implemented Note: The AV and AV pins must always connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY FIGURE 2- MCLR C1 V (2) C6 ...
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... The DD may be beneficial. A typical ) and fast signal transitions must IL is replaced for normal run-time EXAMPLE OF MCLR PIN CONNECTIONS R1 R2 MCLR PIC18FXXJXX JP C1 and V specifications are met and V specifications are met. IL 2010 Microchip Technology Inc. ...
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... Frequency (MHz) Note: Data for Murata GRM21BF50J106ZE01 shown. Measurements at 25° bias. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 2.5 ICSP Pins The PGC and PGD pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes recommended to keep the trace length between the ...
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... Bottom Layer Copper Pour (tied to ground) OSCO GND Devices” OSCI DEVICE PINS SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Primary Oscillator Crystal DEVICE PINS OSC1 ` OSC2 GND ` T1OSO T1OS Oscillator: C2 Top Layer Copper Pour (tied to ground) C2 Oscillator Crystal C1 2010 Microchip Technology Inc. ...
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... MHz Source (INTOSC) INTRC Source 31 kHz (INTRC) 2010 Microchip Technology Inc. PIC18F87J72 FAMILY All of these modes are selected by the user by programming the FOSC<2:0> Configuration bits. In addition, PIC18F87J72 family devices can switch between different clock sources, either under software control or automatically under certain conditions. This ...
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... Phase Locked Loop (PLL) (see Section 3.4.3 “PLL Frequency Multiplier”). (2) R/W-0 R (3) (3) IRCF0 OSTS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (3) (4) (2) (5) Preliminary (1) R-0 R/W-0 R/W-0 (5) (5) IOFS SCS1 SCS0 bit Bit is unknown 2010 Microchip Technology Inc. ...
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... Section 3.4 “External Oscillator Modes”. The secondary oscillators are external clock sources that are not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the 2010 Microchip Technology Inc. PIC18F87J72 FAMILY R/W-0 R/W-0 R/W-0 ...
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... This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 4.1.2 “Entering Power-Managed Modes”. Preliminary 2010 Microchip Technology Inc. ...
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... AN943, “Practical PIC Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” See the notes following Table 3-2 for additional information. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY TABLE 3-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Osc Type Freq ...
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... In this configuration, the PLL is enabled in software and generates a clock output MHz. The operation of INTOSC with the PLL is described in Section 3.5.2 “INTPLL Modes”. Preliminary 2010 Microchip Technology Inc. the PLLEN bit Phase Comparator ...
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... OSC1 functions as RA7 (see Figure 3-6) for digital input and output. • In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6 (see Figure 3-7), both for digital input and output. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY FIGURE 3-6: RA7 F ...
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... To compensate, decrement the OSCTUNE register. If the measured time is much less than the calculated time, the internal oscillator block is running too slow. To compensate, increment the OSCTUNE register. Preliminary 2010 Microchip Technology Inc. ...
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... I/O pin, RA6, direction controlled by TRISA<6> Note: See Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Timer1 oscillator may be operating to support a Real- Time Clock (RTC). Other features may be operating that do not require a device clock source (i.e., MSSP slave, INTx pins and others) ...
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... PIC18F87J72 FAMILY NOTES: DS39979A-page 34 Preliminary 2010 Microchip Technology Inc. ...
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... RC_IDLE 1 11 Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 4.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: • the primary clock, as defined by the FOSC<2:0> ...
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... SEC_RUN mode will not occur. If the Timer1 oscillator is enabled, but not yet running, device clocks will be delayed until the oscillator has started. In such situa- tions, initial oscillator operation is far from stable and unpredictable operation may result. Preliminary 2010 Microchip Technology Inc. ...
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... These intervals are not shown to scale. OST OSC PLL 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Figure 4-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up ...
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... The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n Clock Transition (1) (1) T PLL 1 2 n-1 n Clock Transition PC OSTS Bit Set = 2 ms (approx). These intervals are not shown to scale. Preliminary 2010 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 4.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...
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... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD PC Preliminary 2010 Microchip Technology Inc. ...
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... Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 4.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs ...
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... PIC18F87J72 FAMILY NOTES: DS39979A-page 42 Preliminary 2010 Microchip Technology Inc. ...
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... Ripple Counter INTRC Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip voltage regulator when there is insufficient source voltage to maintain regulation. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 5.1 RCON Register Device Reset events are tracked through the RCON register (Register 5-1) ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39979A-page 44 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 POR BOR bit Bit is unknown 2010 Microchip Technology Inc. ...
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... Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once V rises to the point where DD regulator output is sufficient, the Power-up Timer will execute the additional time delay. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY FIGURE 5- ...
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... PWRT will expire. Bringing MCLR high will begin (Figure 5-5). This is useful for testing purposes synchronize more than one PIC18FXXXX device operating in parallel PWRT T PWRT Preliminary 2010 Microchip Technology Inc. all depict time-out execution immediately , V RISE < PWRT ): CASE 1 DD ...
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... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET 2010 Microchip Technology Inc. PIC18F87J72 FAMILY T PWRT , V RISE > 3. PWRT Preliminary ): CASE 2 DD ...
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... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register ( 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Preliminary STKPTR Register POR BOR STKFUL STKUNF 2010 Microchip Technology Inc. ...
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... See Table 5-1 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY MCLR Resets Power-on Reset, ...
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... Microchip Technology Inc. ...
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... See Table 5-1 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY MCLR Resets Power-on Reset, ...
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... Microchip Technology Inc. ...
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... See Table 5-1 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY MCLR Resets Power-on Reset, ...
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... Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu uuuu uuuu ---- -uu- 2010 Microchip Technology Inc. ...
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... Config. Words Unimplemented Read as ‘0’ Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 6.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter which is capable of addressing a 2-Mbyte program memory space ...
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... Additional details on the device Configuration Words are provided in Section 26.1 “Configuration Bits”. TABLE 6-1: FLASH CONFIGURATION WORD FOR PIC18F87J72 FAMILY DEVICES Program Device Memory (Kbytes) PIC18F86J72 64 PIC18F87J72 128 Preliminary 2010 Microchip Technology Inc. CONFIG1 through Configuration Word Addresses FFF8h to FFFFh 1FFF8h to 1FFFFh ...
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... TOSH TOSL 00h 1Ah 34h 2010 Microchip Technology Inc. PIC18F87J72 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers ...
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... TOS value. R/W-0 R/W-0 R/W-0 SP4 SP3 SP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary POP and Instructions R/W-0 R/W-0 SP1 SP0 bit Bit is unknown 2010 Microchip Technology Inc. ...
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... SUB1 RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 6.1.6 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
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... Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write Execute INST (PC) Execute INST ( Fetch INST ( Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Preliminary Internal Phase Clock Fetch INST ( Flush (NOP) Fetch SUB_1 Execute SUB_1 2010 Microchip Technology Inc. ...
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... MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF 2010 Microchip Technology Inc. PIC18F87J72 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
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... This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. Preliminary 2010 Microchip Technology Inc. ...
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... Note 1: Addresses, F5Ah through F5Fh, are also used by SFRs, but are not part of the Access RAM. Users must always use the complete address, or load the proper SBR value, to access these registers. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Data Memory Map ...
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... This is data RAM which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. Preliminary (2) From Opcode 2010 Microchip Technology Inc. ...
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... Note 1: This is not a physical register. 2: Unimplemented registers are read as ‘0’. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, Resets and interrupts) and those related to the peripheral functions ...
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... N/A 49, 73 N/A 49, 73 ---- xxxx 50, 72 50, 72 xxxx xxxx 50, 62 ---- 0000 N/A 50, 72 N/A 50, 73 N/A 50, 73 N/A 50, 73 N/A 50, 73 50, 72 ---- xxxx 50, 72 xxxx xxxx DC C 50, 70 ---x xxxx C™ Slave mode. See Section 18.4.3.2 “Address 2010 Microchip Technology Inc. ...
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... RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY ...
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... RE1 RE0 xxxx x-xx 52, 117 RD1 RD0 52, 115 xxxx xxxx RC1 RC0 52, 113 xxxx xxxx RB1 RB0 52, 110 xxxx xxxx RA1 RA0 52, 107 xx0x 0000 C™ Slave mode. See Section 18.4.3.2 “Address 2010 Microchip Technology Inc. ...
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... RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY ...
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... Table 27-2 and Table 27-3. Note: The C and DC bits operate as a borrow and digit borrow bit respectively, in subtraction. R/W-x R/W-x R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-x R/W-x (1) ( bit Bit is unknown 2010 Microchip Technology Inc. ...
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... Purpose Register File” location in the Access Bank (Section 6.3.2 “Access Bank”) as the data source for the instruction. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY The Access RAM bit, ‘a’, determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 6.3.1 “ ...
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... RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address. ADDWF, INDF1, 1 FSR1H:FSR1L Preliminary 000h Bank 0 100h Bank 1 200h Bank 2 300h 0 Bank 3 through Bank 13 E00h Bank 14 F00h Bank 15 FFFh Data Memory 2010 Microchip Technology Inc. ...
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... In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 6.4.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases ...
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... Figure 6-9. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 27.2.1 “Extended Instruction Syntax”. Preliminary 2010 Microchip Technology Inc. ...
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... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 000h 060h Bank 0 100h Bank 1 through ...
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... BSR remains unchanged. Direct Addressing, using the BSR to select the data memory bank, operates in the same manner as previously described. Not Accessible Bank 0 Window Bank 1 Bank 2 through Bank 14 Bank 15 SFRs Data Memory Preliminary 00h Bank 1 “Window” 5Fh 60h SFRs FFh Access Bank 2010 Microchip Technology Inc. ...
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... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 7.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... Reset write operation was Reading attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Preliminary Table Latch (8-bit) TABLAT 2010 Microchip Technology Inc. ...
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... Write cycle is complete bit 0 Unimplemented: Read as ‘0’ Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY R/W-0 R/W-x R/W-0 (1) FREE ...
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... Figure 7-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TABLE READ: TBLPTR<21:0> Preliminary TBLPTRL 0 2010 Microchip Technology Inc. ...
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... TBLRD*+ MOVF TABLAT, W MOVWFWORD_EVEN TBLRD*+ MOVF TABLAT, W MOVWFWORD_ODD 2010 Microchip Technology Inc. PIC18F87J72 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. ...
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... The CPU will stall for duration of the erase for T (see parameter D133B Re-enable interrupts. ; load TBLPTR with the base ; address of the memory block ; enable Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Preliminary 2010 Microchip Technology Inc. ...
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... Write the 64 bytes into the holding registers with auto-increment. 7. Set the WREN bit (EECON1<2>) to enable byte writes. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device ...
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... TBLWT holding register. ; loop until buffers are full ; enable write to memory ; disable interrupts ; write 55h ; write 0AAh ; start program (CPU stall) ; re-enable interrupts ; disable write to memory ; done with one write cycle ; if not done replacing the erase block Preliminary 2010 Microchip Technology Inc. ...
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... Sequence MOVLW 0AAh MOVWF EECON2 BSF EECON1, WR BSF INTCON, GIE BCF EECON1, WPROG BCF EECON1, WREN 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 3. Set WPROG to enable single-word write. 4. Set WREN to enable write to memory. 5. Disable interrupts. 6. Write 55h to EECON2. 7. Write 0AAh to EECON2. 8. ...
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... Protection” for details on code protection of Flash program memory. Bit 5 Bit 4 Bit 3 Bit 2 bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) INT0IE RBIE TMR0IF FREE WRERR WREN Preliminary Reset Bit 1 Bit 0 Values on Page INT0IF RBIF — 51 2010 Microchip Technology Inc. ...
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... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply 2010 Microchip Technology Inc. PIC18F87J72 FAMILY EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
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... ARG2H<7> ARG1H:ARG1L (-1 ARG1H<7> ARG2H:ARG2L SIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ARG1H * ARG2H -> ; PRODH:PRODL ; ARG1L * ARG2H -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ; ARG1H * ARG2L -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ; ARG1H:ARG1L neg? ; no, done ; ; ; 2010 Microchip Technology Inc. ...
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... Individual interrupts can be disabled through their corresponding enable bits. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
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... PEIE/GIEL IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP Preliminary 2010 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...
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... Note 1: A mismatch condition will continue to set this bit. Reading PORTB, then waiting one instruction cycle, will end the mismatch condition and allow the bit to be cleared. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Note: Interrupt flag bits are set when an interrupt ...
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... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39979A-page 92 R/W-1 R/W-1 R/W-1 INTEDG2 INTEDG3 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 93
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY R/W-0 ...
Page 94
... R-0 R/W-0 U-0 TX1IF SSPIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 95
... The device voltage is above the regulator’s low-voltage trip point bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software TMR3 register did not overflow bit 0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC18F87J72 FAMILY U-0 R/W-0 R/W-0 — BCLIF LVDIF U = Unimplemented bit, read as ‘ ...
Page 96
... RTCCIF: RTCC Interrupt Flag bit 1 = RTCC interrupt occured (must be cleared in software RTCC interrupt occured DS39979A-page 96 R-0 R/W-0 R/W-0 TX2IF CTMUIF CCP2IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 CCP1IF RTCCIF bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 97
... Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt 2010 Microchip Technology Inc. PIC18F87J72 FAMILY R/W-0 R/W-0 U-0 TX1IE SSPIE — ...
Page 98
... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 Unimplemented: Read as ‘0’ DS39979A-page 98 U-0 R/W-0 R/W-0 — BCLIE LVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary 2010 Microchip Technology Inc. R/W-0 U-0 TMR3IE — bit Bit is unknown ...
Page 99
... Disabled bit 1 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 0 RTCCIE: RTCC Interrupt Enable bit 1 = Enabled 0 = Disabled 2010 Microchip Technology Inc. PIC18F87J72 FAMILY R-0 R/W-0 R/W-0 TX2IE CTMUIE CCP2IE U = Unimplemented bit, read as ‘0’ ...
Page 100
... TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39979A-page 100 R/W-1 R/W-1 U-0 TX1IP SSPIP — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 101
... LVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC18F87J72 FAMILY U-0 R/W-1 R/W-1 — BCLIP LVDIP U = Unimplemented bit, read as ‘0’ ...
Page 102
... Low priority bit 0 RTCCIP: RTCC Interrupt Priority bit 1 = High priority 0 = Low priority DS39979A-page 102 R-1 R/W-1 R/W-1 TX2IP CTMUIP CCP2IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 CCP1IP RTCCIP bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 103
... For details of bit operation, see Register 5-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 5-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 5-1. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘ ...
Page 104
... Example 9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS Preliminary 2010 Microchip Technology Inc. ...
Page 105
... TRIS Latch RD TRIS PORT 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 10.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 10 ...
Page 106
... ADCON1 ; for digital inputs MOVLW 0BFh MOVWF TRISA 5V Preliminary and OSC1/CLKI/RA7 normally INITIALIZING PORTA ; Initialize PORTA by ; clearing output latches ; Alternate method to ; clear output data latches ; Configure A/D ; Value used to initialize ; data direction ; Set RA<7, 5:0> as inputs, ; RA<6> as output 2010 Microchip Technology Inc. ...
Page 107
... Shaded cells are not used by PORTA. Note 1: These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘x’. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY I/O I/O ...
Page 108
... RB<3:2> are multiplexed as CTMU edge inputs. RB<5:0> are also multiplexed with LCD segment drives, controlled by bits in the LCDSE1 and LCDSE3 registers. I/O port functionality is only available when the LCD segments are disabled. Preliminary 2010 Microchip Technology Inc. wake the device from ...
Page 109
... Legend Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2010 Microchip Technology Inc. PIC18F87J72 FAMILY I/O I/O ...
Page 110
... INTEDG3 TMR0IP INT3IE INT2IE INT1IE INT3IF SE13 SE12 SE11 SE10 SE29 SE28 SE27 SE26 Preliminary Reset Bit 1 Bit 0 Values on page RB1 RB0 52 LATB1 LATB0 52 TRISB1 TRISB0 52 INT0IF RBIF 49 INT3IP RBIP 49 INT2IF INT1IF 49 SE09 SE08 51 SE25 SE24 51 2010 Microchip Technology Inc. ...
Page 111
... TRIS bit settings. Note: These pins are configured as digital inputs on any device Reset. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. RC< ...
Page 112
... Asynchronous serial receive data input (EUSART module). DIG Synchronous serial data output (EUSART module); takes priority over port data. ST Synchronous serial data input (EUSART module); user must configure as an input. ANA LCD Segment 28 output; disables all other pin functions. Preliminary 2010 Microchip Technology Inc. ...
Page 113
... CCP2OD CCP1OD LCDSE1 SE15 SE14 LCDSE2 SE23 SE22 LCDSE3 SE31 SE30 LCDSE4 — — Legend: Shaded cells are not used by PORTC. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 LATC5 LATCB4 LATC3 LATC2 TRISC5 ...
Page 114
... EXAMPLE 10-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs Preliminary 2010 Microchip Technology Inc. ...
Page 115
... LATD LATD7 LATD6 TRISD TRISD7 TRISD6 PORTG RDPU REPU LCDSE0 SE07 SE06 Legend: Shaded cells are not used by PORTD. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY I/O I/O Type O DIG LATD<0> data output PORTD<0> data input. O ANA LCD Segment 0 output; disables all other pin functions. ...
Page 116
... MOVWF TRISE for I/O RE6 None Preliminary parts has the function of INITIALIZING PORTE ; Initialize PORTE by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RE<1:0> as inputs ; RE<7:2> as outputs 2010 Microchip Technology Inc. ...
Page 117
... PORTG RDPU REPU TRISG SPIOD CCP2OD CCP1OD LCDCON LCDEN SLPEN LCDSE3 SE31 SE30 Legend: Shaded cells are not used by PORTE. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY I/O I/O Type O DIG LATE<0> data output PORTE<0> data input. I ANA LCD module bias voltage input. ...
Page 118
... MOVLW 07h ; MOVWF CMCON ; Turn off comparators MOVLW 0Fh ; MOVWF ADCON1 ; Set PORTF as digital I/O MOVLW 0CEh ; Value used to ; initialize data ; direction MOVWF TRISF ; Set RF3:RF1 as inputs ; RF5:RF4 as outputs ; RF7:RF6 as inputs Preliminary 2010 Microchip Technology Inc. ...
Page 119
... Legend Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2010 Microchip Technology Inc. PIC18F87J72 FAMILY I/O I/O ...
Page 120
... CIS CM2 CVRR CVRSS CVR3 CVR2 SE21 SE20 SE19 SE18 SE29 SE28 SE27 SE26 Preliminary Reset Bit 1 Bit 0 Values on page RF1 — 52 LATF1 — 52 TRISF1 — 52 PCFG1 PCFG0 51 CM1 CM0 51 CVR1 CVR0 51 SE17 SE16 51 SE25 SE24 51 2010 Microchip Technology Inc. ...
Page 121
... The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Although the port itself is only five bits wide, the PORTG<7:5> bits are still implemented to control the weak pull-ups on the I/O ports associated with PORTD, PORTE and PORTJ ...
Page 122
... DIG RTCC output. Bit 5 Bit 4 Bit 3 Bit 2 RJPU RG4 RG3 RG2 — LATG4 LATG3 LATG2 TRISG3 TRISG2 SE29 SE28 SE27 SE26 Preliminary Description Reset Bit 1 Bit 0 Values on page RG1 RG0 52 LATG1 LATG0 52 TRISG1 TRISG0 52 SE25 SE24 51 2010 Microchip Technology Inc. ...
Page 123
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value 2010 Microchip Technology Inc. PIC18F87J72 FAMILY The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...
Page 124
... Sync with Internal TMR0L Clocks Delay Preliminary ). There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus 2010 Microchip Technology Inc. ...
Page 125
... RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 11.3.1 ...
Page 126
... PIC18F87J72 FAMILY NOTES: DS39979A-page 126 Preliminary 2010 Microchip Technology Inc. ...
Page 127
... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 2010 Microchip Technology Inc. PIC18F87J72 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 128
... Special Event Trigger) Preliminary 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus 2010 Microchip Technology Inc. ...
Page 129
... PIC18F87J72 27 pF T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 12-1 for additional information about capacitor selection. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Oscillator Freq. Type LP 32.768 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 130
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. Preliminary 2010 Microchip Technology Inc. ...
Page 131
... Timer1 Register High Byte T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...
Page 132
... PIC18F87J72 FAMILY NOTES: DS39979A-page 132 Preliminary 2010 Microchip Technology Inc. ...
Page 133
... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
Page 134
... Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TX1IF SSPIF TX1IE SSPIE TX1IP SSPIP Preliminary Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 49 — TMR2IF TMR1IF 52 — TMR2IE TMR1IE 52 — TMR2IP TMR1IP 2010 Microchip Technology Inc. ...
Page 135
... OSC bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 2010 Microchip Technology Inc. PIC18F87J72 FAMILY A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1) ...
Page 136
... RC1/T1OSI/SEG32 and 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR3L Write TMR3L 8 8 TMR3H 8 8 Internal Data Bus 2010 Microchip Technology Inc. ...
Page 137
... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
Page 138
... PIC18F87J72 FAMILY NOTES: DS39979A-page 138 Preliminary 2010 Microchip Technology Inc. ...
Page 139
... Input from Timer1 Oscillator Internal RC Alarm Event 2010 Microchip Technology Inc. PIC18F87J72 FAMILY The RTCC module is intended for applications, where accurate time must be maintained for an extended period with minimum to no intervention from the CPU. The module is optimized for low-power usage in order to provide extended battery life while keeping track of time ...
Page 140
... Alarm Value Registers • ALRMVALH and ALRMVALL – Can access the following registers: - ALRMMNTH - ALRMDAY - ALRMWD - ALRMHR - ALRMMIN - ALRMSEC Note: The RTCVALH and RTCVALL registers can be accessed through RTCRPT<1:0>. ALRMVALH and ALRMVALL can be accessed through ALRMPTR<1:0>. Preliminary 2010 Microchip Technology Inc. ...
Page 141
... The RTCCFG register is only affected by a POR. For Resets other than POR, RTCC will continue to run even if the device is in Reset write to the RTCEN bit is only allowed when RTCWREN = 1. 3: This bit is read-only cleared to ‘0’ write to the lower half of the MINSEC register. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY (1) R-0 R-0 R/W-0 ...
Page 142
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 R/W-0 (1) — — RTSECSEL1 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary R/W-0 R/W-0 CAL1 CAL0 bit Bit is unknown R/W-0 U-0 (1) RTSECSEL0 — bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 143
... The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’. ALRMVALH ALRMMIN 01 = ALRMWD 10 = ALRMMNTH 11 = Unimplemented ALRMVALL ALRMSEC 01 = ALRMHR 10 = ALRMDAY 11 = Unimplemented 2010 Microchip Technology Inc. PIC18F87J72 FAMILY R/W-0 R/W-0 R/W-0 AMASK2 AMASK1 AMASK0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared th , once every four years) ...
Page 144
... R/W-x R/W-x YRTEN0 YRONE3 YRONE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 ARPT1 ARPT0 bit Bit is unknown U-0 U-0 — — bit Bit is unknown R/W-x R/W-x YRONE1 YRONE0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 145
... Bit is set bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from Note 1: A write to this register is only allowed when RTCWREN = 1. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY (1) R/W-x R/W-x R/W-x MTHTEN0 MTHONE3 MTHONE2 U = Unimplemented bit, read as ‘ ...
Page 146
... R/W-x R/W-x SECTEN0 SECONE3 SECONE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-x R/W-x HRONE1 HRONE0 bit Bit is unknown R/W-x R/W-x MINONE1 MINONE0 bit Bit is unknown R/W-x R/W-x SECONE1 SECONE0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 147
... Bit is set bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from Note 1: A write to this register is only allowed when RTCWREN = 1. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY (1) R/W-x R/W-x R/W-x MTHTEN0 MTHONE3 MTHONE2 U = Unimplemented bit, read as ‘ ...
Page 148
... R/W-x R/W-x SECTEN0 SECONE3 SECONE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-x R/W-x HRONE1 HRONE0 bit Bit is unknown R/W-x R/W-x MINONE1 MINONE0 bit Bit is unknown R/W-x R/W-x SECONE1 SECONE0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 149
... FIGURE 15-3: ALARM DIGIT FORMAT Hours (24-hour format) 0-2 0-9 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 15.2 Operation 15.2.1 REGISTER INTERFACE The register interface for the RTCC and alarm values is implemented using the Binary Coded Decimal (BCD) format. This simplifies the firmware when using the module, as each of the digits is contained within its own 4-bit value (see Figure 15-2 and Figure 15-3) ...
Page 150
... Note 1: See Section 15.2.4 “Leap Year”. Preliminary One-Second Clock (1) Half Second Month Year DAY OF WEEK SCHEDULE Day of Week DAY TO MONTH ROLLOVER SCHEDULE Maximum Day Field 31 ( 2010 Microchip Technology Inc. ...
Page 151
... This firmware solution would consist of reading each register twice and then comparing the two values. If the two values matched, then a rollover did not occur. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 15.2.7 WRITE LOCK In order to perform a write to any of the RTCC Timer registers, the RTCWREN bit (RTCCFG< ...
Page 152
... To avoid this, only change the timer and alarm values while the alarm is disabled (ALRMEN = 0 recom- mended ALRMRPT registers and CHIME bit be changed when RTCSYNC = 0. Preliminary that the ALRMCFG and 2010 Microchip Technology Inc. ...
Page 153
... ALRMRPT register with FFh. After each alarm is issued, the ALRMRPT register is decremented by one. Once the register has reached ‘00’, the alarm will be issued one last time. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Day of the Week Month ...
Page 154
... POR. Once the device exits the POR state, the clock registers should be reloaded with the desired values. The timer prescaler values can be reset only by writing to the SECONDS register. No device Reset can affect the prescalers. Preliminary 2010 Microchip Technology Inc. ...
Page 155
... ALRMVALH Alarm Value High Register Window Based on ALRMPTR<1:0> ALRMVALL Alarm Value Low Register Window Based on ALRMPTR<1:0> Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 80-pin devices. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Bit 4 Bit 3 Bit 2 RTCSYNC ...
Page 156
... PIC18F87J72 FAMILY NOTES: DS39979A-page 156 Preliminary 2010 Microchip Technology Inc. ...
Page 157
... PWM mode Note 1: CCPxM<3:0> = 1011 will only reset the timer and not start an A/D conversion on a CCP1 match. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Each CCP module contains two 8-bit registers that can operate as two 8-bit Capture registers, two 8-bit Compare registers or two PWM Master/Slave Duty Cycle registers ...
Page 158
... TMR1 TMR3 CCP1 CCP2 TMR2 Timer3 is used for all capture and compare operations for all CCP modules. Timer2 is used for PWM operations for all CCP modules. Modules may share either timer resource as a common time base. 2010 Microchip Technology Inc. ...
Page 159
... Capture PWM None Compare PWM None PWM Capture None PWM Compare None PWM PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt). 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Interaction Preliminary DS39979A-page 159 ...
Page 160
... Turn CCP module off ; Load WREG with the ; new prescaler mode ; value and CCP ON ; Load CCP2CON with ; this value TMR3H TMR3L TMR3 Enable CCPR1H CCPR1L TMR1 Enable TMR1H TMR1L TMR3H TMR3L TMR3 Enable CCPR2H CCPR2L TMR1 Enable TMR1H TMR1L 2010 Microchip Technology Inc. ...
Page 161
... TMR3H TMR3L T3CCP1 Comparator CCPR2H CCPR2L 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 16.3.3 SOFTWARE INTERRUPT MODE When the Generate Software Interrupt mode is chosen (CCP2M<3:0> = 1010), the CCP2 pin is not affected. Only a CCP interrupt is generated, if enabled, and the CCP2IE bit is set. ...
Page 162
... CCP2M2 CCP2M1 CCP2M0 Preliminary Reset Bit 1 Bit 0 Values on Page INT0IF RBIF 49 PD POR BOR 50 CCP1IF RTCCIF 52 CCP1IE RTCCIE 52 CCP1IP RTCCIP 52 TMR3IF — 52 TMR3IE — 52 TMR3IP — 52 TRISC1 TRISC0 52 — TRISE1 TRISE0 52 TRISG1 TRISG0 TMR1CS TMR1ON TMR3CS TMR3ON 2010 Microchip Technology Inc. ...
Page 163
... The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY A PWM output (Figure 16-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period) ...
Page 164
... PWM period, the CCP2 pin will not be cleared. 9.77 kHz 39.06 kHz FFh FFh Preliminary F OSC log --------------- F PWM = -----------------------------bits 2 log 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 2010 Microchip Technology Inc. ...
Page 165
... CCPR2H Capture/Compare/PWM Register 2 High Byte CCP2CON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 3. Make the CCP2 pin an output by clearing the appropriate TRIS bit. 4. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON ...
Page 166
... PIC18F87J72 FAMILY NOTES: DS39979A-page 166 Preliminary 2010 Microchip Technology Inc. ...
Page 167
... LCD Clock T13CKI Source Select INTRC Oscillator INTOSC Oscillator 2010 Microchip Technology Inc. PIC18F87J72 FAMILY The LCD driver module supports these features: • Direct driving of LCD panel • On-chip bias generator with dedicated charge pump to support a range of fixed and variable bias options • ...
Page 168
... Maximum Number Multiplex Type of Pixels Static (COM0) 33 1/2 (COM1:COM0) 66 1/3 (COM2:COM0) 99 1/4 (COM3:COM0) 132 Preliminary register, shown in Register 17-2, (LCDSE4:LCDSE0), listed in R/W-0 R/W-0 CS0 LMUX1 LMUX0 bit Bit is unknown Bias Type Static 1/2 or 1/3 1/2 or 1/3 1/3 2010 Microchip Technology Inc. ...
Page 169
... Microchip Technology Inc. PIC18F87J72 FAMILY R-0 R/W-0 R/W-0 WA LP3 LP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 170
... LCDSE1 LCDSE2 LCDSE3 (1) LCDSE4 Note 1: Only LCDSE4<0> (SEG32) is implemented. DS39979A-page 170 R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Segments Preliminary R/W-0 R/W-0 SE SE(n) bit Bit is unknown 7:0 15:8 23:16 31:24 32 2010 Microchip Technology Inc. ...
Page 171
... LCDDATA4 32 S32C0 Note 1: Only bit<0> of these registers is implemented. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Individual LCDDATA bits are named by the convention “SxxCy”, with “xx” as the segment number and “y” as the common number. The relationship is summarized in Table 17-2. The prototype LCDDATA register is shown in Register 17-4 ...
Page 172
... LCD clock source or for any other purpose, LCD Segment 32 becomes unavailable. LCDPS<3:0> 4 ÷4 00 ÷2 01 1:1 to 1:16 Programmable 10 Prescaler ÷256 10 01 Preliminary /4 frequency of 8 MHz). OSC /4 clock OSC COM0 ÷32 ÷ COM1 or COM2 Ring Counter ÷8192 COM3 31 kHz Clock to LCD Charge Pump 2010 Microchip Technology Inc. ...
Page 173
... CKSEL<1:0>: Regulator Clock Source Select bits 11 = INTRC 10 = INTOSC 8 MHz source 01 = Timer1 oscillator 00 = LCD regulator disabled 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 17.3.2 LCD VOLTAGE REGULATOR The purpose of the LCD regulator is to provide proper bias voltage and good contrast for the LCD, regardless of V levels ...
Page 174
... M1 (Regulator without Boost the voltage BIAS for the application is expected to DD (Figure 17-3 with M0, changing BIAS will also change; where in BIAS is constant. BIAS FLY (1) 0.47 µ (1) 0.47 µF C1 (1) 0.47 µF C0 (1) 0.47 µF Mode 1 BIAS DD 2010 Microchip Technology Inc. ...
Page 175
... LCDBIAS3 Note 1: These values are provided for design guidance only; they should be optimized for the application by the designer based on the actual LCD specifications. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY configuration of the resistor ladder. Most applications using M2 will use a 1/3 or 1/2 Bias type. While Static ...
Page 176
... M3 is selected by clearing the CKSEL<1:0> and CPEN bits (2) 10 k 10 k Static Bias 1/2 Bias Bias Type Static 1/2 Bias 1 1 Preliminary (1) (1) 10 k (1) 10 k (1) (1) 10 k 1/3 Bias 1/3 Bias 2010 Microchip Technology Inc. ...
Page 177
... LCDBIAS pins can be changed to increase or decrease current. As always, any changes should be evaluated in the actual circuit for its impact on the application. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 17.4 LCD Multiplex Types The LCD driver module can be configured into four multiplex types: • ...
Page 178
... Thus, always take care to see that the V on all pixels is ‘0’ whenever Sleep mode is invoked. Figure 17-6 through Figure 17-16 provide waveforms for static, half multiplex, one-third multiplex and quarter multiplex drives for Type-A and Type-B waveforms. Preliminary on all the pixels DC DC 2010 Microchip Technology Inc. ...
Page 179
... FIGURE 17-6: TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE COM0 2010 Microchip Technology Inc. PIC18F87J72 FAMILY COM0 SEG0 SEG1 COM0-SEG0 COM0-SEG1 1 Frame Preliminary DS39979A-page 179 ...
Page 180
... PIC18F87J72 FAMILY FIGURE 17-7: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 DS39979A-page 180 COM0 COM1 SEG0 SEG1 1 Frame Preliminary 2010 Microchip Technology Inc. ...
Page 181
... FIGURE 17-8: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 2010 Microchip Technology Inc. PIC18F87J72 FAMILY COM0 COM1 SEG0 SEG1 2 Frames Preliminary DS39979A-page 181 ...
Page 182
... PIC18F87J72 FAMILY FIGURE 17-9: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 DS39979A-page 182 COM0 COM1 SEG0 SEG1 1 Frame Preliminary 2010 Microchip Technology Inc. ...
Page 183
... FIGURE 17-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 2010 Microchip Technology Inc. PIC18F87J72 FAMILY COM0 COM1 SEG0 SEG1 2 Frames Preliminary DS39979A-page 183 ...
Page 184
... PIC18F87J72 FAMILY FIGURE 17-11: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 DS39979A-page 184 COM0 COM1 COM2 SEG0 SEG2 SEG1 Preliminary Frame 2010 Microchip Technology Inc. ...
Page 185
... FIGURE 17-12: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 2010 Microchip Technology Inc. PIC18F87J72 FAMILY COM0 COM1 COM2 SEG0 SEG1 Preliminary Frames DS39979A-page 185 ...
Page 186
... PIC18F87J72 FAMILY FIGURE 17-13: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE COM2 COM1 COM0 DS39979A-page 186 COM0 COM1 COM2 SEG0 SEG2 SEG1 COM0-SEG0 COM0-SEG1 Preliminary Frame 2010 Microchip Technology Inc. ...
Page 187
... FIGURE 17-14: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 2010 Microchip Technology Inc. PIC18F87J72 FAMILY COM0 COM1 COM2 SEG0 SEG1 Preliminary Frames DS39979A-page 187 ...
Page 188
... PIC18F87J72 FAMILY FIGURE 17-15: TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 DS39979A-page 188 COM0 COM1 COM2 COM3 SEG0 SEG1 1 Frame Preliminary 2010 Microchip Technology Inc. ...
Page 189
... FIGURE 17-16: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 2010 Microchip Technology Inc. PIC18F87J72 FAMILY COM0 COM1 COM2 COM3 SEG0 SEG1 2 Frames Preliminary DS39979A-page 189 ...
Page 190
... The interrupt is not generated when the Type-A waveform is selected and when the ). New data Type-B with no multiplex (static) is selected. LCD Interrupt Occurs 2 Frames T FWR Frame Boundary /2 CY /4) – ns) FRAME CY /4) – ns) FRAME CY Preliminary Controller Accesses Next Frame Data FINT Frame Boundary 2010 Microchip Technology Inc. ...
Page 191
... COM0 COM1 COM2 SEG0 2 Frames SLEEP 2010 Microchip Technology Inc. PIC18F87J72 FAMILY internal oscillators (either INTRC or INTOSC as the default system clock). While in Sleep, the LCD data cannot be changed. The LCD module current consumption will not decrease in this mode; however, the overall consumption of the device will be lower due to shutdown of the core and other peripheral functions ...
Page 192
... CKSEL<1:0> bits. 7. Clear LCD Interrupt Flag, LCDIF (PIR3<6>), and if desired, enable the interrupt by setting the LCDIE bit (PIE3<6>). 8. Enable the LCD module by setting the LCDEN bit (LCDCON<7>). Preliminary 2010 Microchip Technology Inc. regulator by setting level using the BIAS<2:0> the MODE13 bit ...
Page 193
... These registers or individual bits are unimplemented on PIC18F86J72 devices. Note: When the device enters Sleep mode while operating in Bias modes M1, be sure that the bias capacitors are fully discharged in order to get the lowest Sleep current. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Bit 5 Bit 4 ...
Page 194
... PIC18F87J72 FAMILY NOTES: DS39979A-page 194 Preliminary 2010 Microchip Technology Inc. ...
Page 195
... MSSP module 2 is operated in SPI mode. Additional details are provided under the individual sections. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 18.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four ...
Page 196
... SSPIF interrupt is set. During transmission, double-buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary the SSPBUF is not R0 R bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 197
... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I 2010 Microchip Technology Inc. PIC18F87J72 FAMILY R/W-0 R/W-0 (2) (3) ...
Page 198
... To prevent lost data in Master mode, read SSPBUF after each transmission to clear the BF bit. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the SSPSTAT register indicates the various status conditions. Preliminary 2010 Microchip Technology Inc. ...
Page 199
... Shift Register (SSPSR) LSb MSb PROCESSOR 1 2010 Microchip Technology Inc. PIC18F87J72 FAMILY to a higher level through an external pull-up resistor, and allows the output to communicate with external circuits without the need for additional level shifters. The open-drain output option is controlled by the SPIOD bit (TRISG< ...
Page 200
... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 5 bit 4 bit 3 bit 2 bit 1 Preliminary ) Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2 2010 Microchip Technology Inc. ...