PIC18F87K22-E/PT Microchip Technology, PIC18F87K22-E/PT Datasheet
PIC18F87K22-E/PT
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PIC18F87K22-E/PT Summary of contents
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... Enhanced Flash Microcontrollers 2009-2011 Microchip Technology Inc. PIC18F87K22 Family 64/80-Pin, High-Performance, with 12-Bit A/D and nanoWatt XLP Technology Data Sheet DS39960D ...
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... Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009-2011, Microchip Technology Incorporated, Printed in the U ...
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... PIC18F86K22 64K 32,768 PIC18F87K22 128K 65,536 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY Special Microcontroller Features: • Operating Voltage Range: 1.8V to 5.5V • On-Chip 3.3V Regulator • Operating Speed MHz • 128 Kbytes On-Chip Flash Program Memory • Data EEPROM of 1,024 Bytes • ...
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... PIC18F87K22 FAMILY Peripheral Highlights: • Ten CCP/ECCP modules seven Capture/Compare/PWM (CCP) modules - Three Enhanced Capture/Compare/PWM (ECCP) modules • Eleven 8/16-Bit Timer/Counter modules: - Timer0 – 8/16-bit timer/counter with 8-bit programmable prescaler - Timer1,3 – 16-bit timer/counter - Timer2,4,6,8 – 8-bit timer/counter - Timer5,7 – 16-bit timer/counter for 64k and 128k parts - Timer10,12 – ...
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... RF6/AN11/C1INA RF5/AN10/CV /C1INB REF RF4/AN9/C2INA RF3/AN8/C2INB/CTMUI RF2/AN7/C1OUT Note 1: The ECCP2 pin placement depends on the CCP2MX Configuration bit setting and whether the device is in Microcontroller or Extended Microcontroller mode. 2: Not available on the PIC18F65K22 and PIC18F85K22 devices. 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY ...
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... PIC18F87K22 FAMILY Pin Diagrams – PIC18F8XK22 80-Pin TQFP RH2/AN21/A18 RH3/AN20/A19 RE1/P2C/WR/AD9 RE0/P2D/RD/AD8 RG0/ECCP3/P3A RG1/TX2/CK2/AN19/C3OUT RG2/RX2/DT2/AN18/C3INA RG3/CCP4/AN17/P3D/C3INB MCLR/RG5 (2) RG4/RTCC/T7CKI /T5G/CCP5/AN16/P1D/C3INC DDCORE CAP RF7/AN5/SS1 RF6/AN11/C1INA RF5/AN10/C1INB RF4/AN9/C2INA RF3/AN8/C2INB/CTMUI RF2/AN7/C1OUT (3) RH7/CCP6 /P1B/AN15 (3) RH6/CCP7 /P1C/AN14/C1INC Note 1: The ECCP2 pin placement depends on the CCP2MX Configuration bit setting and whether the device is in Microcontroller or Extended Microcontroller mode ...
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... Instruction Set Summary .......................................................................................................................................................... 431 30.0 Development Support............................................................................................................................................................... 481 31.0 Electrical Characteristics .......................................................................................................................................................... 485 32.0 Packaging Information.............................................................................................................................................................. 525 Appendix A: Revision History............................................................................................................................................................. 533 Appendix B: Migration From PIC18F87J11 and PIC18F8722 to PIC18F87K22................................................................................ 534 Index .................................................................................................................................................................................................. 535 The Microchip Web Site ..................................................................................................................................................................... 547 Customer Change Notification Service .............................................................................................................................................. 547 Customer Support .............................................................................................................................................................................. 547 Reader Response ...
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... PIC18F87K22 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...
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... Core Features 1.1.1 nanoWatt TECHNOLOGY All of the devices in the PIC18F87K22 family incorpo- rate a range of features that can significantly reduce power consumption during operation. Key items include: • Alternate Run Modes: By clocking the controller from the Timer1 source or the Internal RC oscilla- tor, power consumption during code execution can be reduced ...
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... PIC18F85K22). Those devices have two less CCPs and three less timers. The PIC18F87K22 family is also largely pin compatible with other PIC18 families, such as the PIC18F8720 and PIC18F8722 and the PIC18F85J11. This allows a new dimension to the evolution of applications, allowing developers to select different price points within Microchip’ ...
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... Details on Individual Family Members Devices in the PIC18F87K22 family are available in 64-pin and 80-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and The devices are differentiated from each other in these ways: • Flash Program Memory: - PIC18FX5K22 (PIC18F65K22 and PIC18F85K22) – ...
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... PIC18F87K22 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC18F6XK22 (64-PIN DEVICES) Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources I/O Ports Parallel Communications Timers Comparators CTMU RTCC Capture/Compare/PWM (CCP) Modules Enhanced CCP (ECCP) Modules Serial Communications ...
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... I/O port pin descriptions. Note 1: RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see 2: Configurations”. Unimplemented on the PIC18F65K22. 3: 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY Data Bus<8> Data Latch 8 8 Data Memory (2/4 Kbytes) PCLATU ...
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... PIC18F87K22 FAMILY FIGURE 1-2: PIC18F8XK22 (80-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic 21 20 Address Latch Program Memory Data Latch 8 Table Latch ROM Latch Instruction Bus <16> AD15:0, A19:16 (Multiplexed with PORTD, PORTE and PORTH) Instruction Decode and Timing Power-up OSC2/CLKO Generation ...
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... Not available on PIC18F65K22 and PIC18F85K22 devices. 3: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit 4: (CONFIG3H<1>). 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY Buffer Type Type Master Clear (input) or programming voltage (input This pin is an active-low Reset to the device. ...
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... PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Pin Name QFN/TQFP RA0/AN0/ULPWU 24 RA0 AN0 ULPWU RA1/AN1 23 RA1 AN1 RA2/AN2 REF RA2 AN2 V - REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI 28 RA4 T0CKI RA5/AN4/T1CKI/T3G/ 27 HLVDIN RA5 AN4 T1CKI T3G ...
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... The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit 4: (CONFIG3H<1>). 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. ...
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... PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Pin Name QFN/TQFP RC0/SOSCO/SCLKI 30 RC0 SOSCO SCLKI RC1/SOSCI/ECCP2/P2A 29 RC1 SOSCI (1) ECCP2 P2A RC2/ECCP1/P1A 33 RC2 ECCP1 P1A RC3/SCK1/SCL1 34 RC3 SCK1 (4) SCL1 RC4/SDI1/SDA1 35 RC4 SDI1 (4) SDA1 RC5/SDO1 36 RC5 SDO1 RC6/TX1/CK1 31 RC6 ...
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... Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K22 and PIC18F85K22 devices. 3: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit 4: (CONFIG3H<1>). 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY Buffer Type Type PORTD is a bidirectional I/O port. I/O ST Digital I/O. ...
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... PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Pin Name QFN/TQFP RE0/RD/P2D 2 RE0 RD P2D RE1/WR/P2C 1 RE1 WR P2C RE2/CS/P2B/CCP10 64 RE2 CS P2B (3) CCP10 RE3/P3C/CCP9/REFO 63 RE3 P3C (3,4) CCP9 REFO RE4/P3B/CCP8 62 RE4 P3B (4) CCP8 RE5/P1C/CCP7 61 RE5 P1C (4) CCP7 RE6/P1B/CCP6 60 RE6 ...
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... Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K22 and PIC18F85K22 devices. 3: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit 4: (CONFIG3H<1>). 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY Buffer Type Type PORTF is a bidirectional I/O port. I/O ST Digital I/O. ...
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... PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Pin Name QFN/TQFP RG0/ECCP3/P3A 3 RG0 ECCP3 P3A RG1/TX2/CK2/AN19/ 4 C3OUT RG1 TX2 CK2 AN19 C3OUT RG2/RX2/DT2/AN18/ 5 C3INA RG2 RX2 DT2 AN18 C3INA RG3/CCP4/AN17/P3D/ 6 C3INB RG3 CCP4 AN17 P3D C3INB RG4/RTCC/T7CKI/T5G/ ...
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... Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K22 and PIC18F85K22 devices. 3: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit 4: (CONFIG3H<1>). 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY Buffer Type Type P — Ground reference for logic and I/O pins. P — ...
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... PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS Pin Number Pin Name TQFP 9 MCLR/RG5 RG5 MCLR OSC1/CLKI/RA7 49 OSC1 CLKI RA7 OSC2/CLKO/RA6 50 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power C™/SMBus Default assignment for ECCP2 when the CCP2MX Configuration bit is set. ...
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... Not available on PIC18F65K22 and PIC18F85K22 devices. 3: PSP is available only in Microcontroller mode. 4: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit 5: (CONFIG3H<1>). 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O ...
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... PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RB0/INT0/FLT0 58 RB0 INT0 FLT0 RB1/INT1 57 RB1 INT1 RB2/INT2/CTED1 56 RB2 INT2 CTED1 RB3/INT3/CTED2/ 55 ECCP2/P2A RB3 INT3 CTED2 ECCP2 P2A RB4/KBI0 54 RB4 KBI0 RB5/KBI1/T3CKI/T1G 53 RB5 KBI1 T3CKI T1G RB6/KBI2/PGC ...
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... Not available on PIC18F65K22 and PIC18F85K22 devices. 3: PSP is available only in Microcontroller mode. 4: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit 5: (CONFIG3H<1>). 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O ...
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... PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RD0/PSP0/CTPLS/AD0 72 RD0 (4) PSP0 CTPLS AD0 RD1/T5CKI/T7G/PSP1/AD1 69 RD1 T5CKI T7G (4) PSP1 AD1 RD2/PSP2/AD2 68 RD2 (4) PSP2 AD2 RD3/PSP3/AD3 67 RD3 (4) PSP3 AD3 RD4/SDO2/PSP4/AD4 66 RD4 SDO2 (4) PSP4 AD4 RD5/SDI2/SDA2/PSP5/ 65 AD5 RD5 ...
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... Not available on PIC18F65K22 and PIC18F85K22 devices. 3: PSP is available only in Microcontroller mode. 4: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit 5: (CONFIG3H<1>). 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY Pin Buffer Type Type I/O ST Digital I/O. ...
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... PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RE0/P2D/RD/AD8 4 RE0 P2D (4) RD AD8 RE1/P2C/WR/AD9 3 RE1 P2C (4) WR AD9 RE2/P2B/CCP10/CS/ 78 AD10 RE2 P2B (3) CCP10 (4) CS AD10 RE3/P3C/CCP9/REFO 77 AD11 RE3 P3C (3,5) CCP9 REFO AD11 RE4/P3B/CCP8/AD12 76 RE4 ...
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... Not available on PIC18F65K22 and PIC18F85K22 devices. 3: PSP is available only in Microcontroller mode. 4: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit 5: (CONFIG3H<1>). 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY Pin Buffer Type Type I/O ST Digital I/O. ...
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... PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RF1/AN6/C2OUT/CTDIN 23 RF1 AN6 C2OUT CTDIN RF2/AN7/C1OUT 18 RF2 AN7 C1OUT RF3/AN8/C2INB/CTMUI 17 RF3 AN8 C2INB CTMUI RF4/AN9/C2INA 16 RF4 AN9 C2INA RF5/AN10/C1INB 15 RF5 AN10 C1INB RF6/AN11/C1INA 14 RF6 AN11 C1INA RF7/AN5/SS1 ...
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... Not available on PIC18F65K22 and PIC18F85K22 devices. 3: PSP is available only in Microcontroller mode. 4: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit 5: (CONFIG3H<1>). 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY Pin Buffer Type Type PORTG is a bidirectional I/O port. I/O ST Digital I/O ...
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... PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RH0/AN23/A16 79 RH0 AN23 A16 RH1/AN22/A17 80 RH1 AN22 A17 RH2/AN21/A18 1 RH2 AN21 A18 RH3/AN20/A19 2 RH3 AN20 A19 RH4/CCP9/P3C/AN12/ 22 C2INC RH4 (3,5) CCP9 P3C AN12 C2INC RH5/CCP8/P3B/AN13/ 21 C2IND RH5 ...
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... Not available on PIC18F65K22 and PIC18F85K22 devices. 3: PSP is available only in Microcontroller mode. 4: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit 5: (CONFIG3H<1>). 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY Pin Buffer Type Type I/O ST Digital I/O. ...
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... PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RJ0/ALE 62 RJ0 ALE RJ1/OE 61 RJ1 OE RJ2/WRL 60 RJ2 WRL RJ3/WRH 59 RJ3 WRH RJ4/BA0 39 RJ4 BA0 RJ5/CE 40 RJ5 CE RJ6/LB 41 RJ6 LB RJ7/UB 42 RJ7 UB V 11, 31, 51 32, 48 ENVREG DDCORE CAP V DDCORE ...
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... GUIDELINES FOR GETTING STARTED WITH PIC18FXXKXX MICROCONTROLLERS 2.1 Basic Connection Requirements Getting started with the PIC18F87K22 family family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: • All V ...
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... PIC18F87K22 FAMILY 2.2 Power Supply Pins 2.2.1 DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher ...
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... ECJ-4YB1C106K Murata GRM32DR71C106KA01L Murata GRM31CR61C106KC31L 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY Some PIC18FXXKXX families, or some devices within a family, do not provide the option of enabling or disabling the on-chip voltage regulator: • Some devices (with the name, PIC18LFXXKXX) permanently disable the voltage regulator. ...
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... PIC18F87K22 FAMILY 2.4.1 CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the inter- nal voltage regulator of this microcontroller ...
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... Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ kΩ resistor unused pins and drive the SS output to logic low. 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY FIGURE 2-5: (refer to Single-Sided and In-Line Layouts: for details). Copper Pour ...
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... PIC18F87K22 FAMILY NOTES: DS39960D-page 42 2009-2011 Microchip Technology Inc. ...
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... OSCILLATOR CONFIGURATIONS 3.1 Oscillator Types The PIC18F87K22 family of devices can be operated in the following oscillator modes: • EC External clock, RA6 available • ECIO External clock, clock out RA6 (F on RA6) • HS High-Speed Crystal/Resonator • XT Crystal/Resonator • LP Low-Power Crystal • RC External Resistor/Capacitor, RA6 available • ...
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... EC1IO) EC2 (medium power) (EC2 & EC2IO) EC3 (high power) (EC3 & EC3IO) HS1 (medium power) HS2 (high power (External) INTIO FIGURE 3-1: PIC18F87K22 FAMILY CLOCK DIAGRAM SOSCO SOSCI OSC2 OSC1 HF INTOSC 16 MHz to 31 kHz MF INTOSC 500 kHz to 31 kHz LF INTOSC ...
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... INTSRC = OSCTUNE<7> and MFIOSEL = OSCCON2<0>. 5: Lowest power option for an internal source. 6: 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY The OSCTUNE register tuning and operation of the internal oscillator block. It also implements the PLLEN bit which controls the operation of the Phase Locked Loop (PLL) (see Frequency Multiplier” ...
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... PIC18F87K22 FAMILY REGISTER 3-1: OSCCON: OSCILLATOR CONTROL REGISTER bit 2 HFIOFS: INTOSC Frequency Stable bit 1 = HF-INTOSC oscillator frequency is stable 0 = HF-INTOSC oscillator frequency is not stable bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block (LF-INTOSC, MF-INTOSC or HF-INTOSC SOSC oscillator 00 = Default primary oscillator (OSC1/OSC2 or HF-INTOSC with or without PLL; defined by the FOSC< ...
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... Center frequency; fast RC oscillator is running at the calibrated frequency 111111 • • • • 100000 = Minimum frequency 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 ...
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... Monitor. The internal oscillator block is discussed in more detail in Section 3.6 “Internal Oscillator Block”. The PIC18F87K22 family includes features that allow the device clock source to be switched from the main oscillator, chosen by device configuration, to one of the alternate clock sources. When an alternate clock source is enabled, various power-managed operating modes are available ...
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... SCS<1:0> bits, at any given time. 3.3.3 OSCILLATOR TRANSITIONS PIC18F87K22 family devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source ...
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... PIC18F87K22 FAMILY 3.5 External Oscillator Modes 3.5.1 CRYSTAL OSCILLATOR/CERAMIC RESONATORS (HS MODES HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 3-4 shows connections. The oscillator design requires the use of a crystal rated for parallel resonant operation. ...
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... EMI due to high-frequency crystals, or users who require higher clock speeds from an internal oscillator. 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY 3.5.3.1 HSPLL and ECPLL Modes The HSPLL and ECPLL modes provide the ability to selectively run the device at four times the external oscillating source to produce frequencies MHz ...
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... PIC18F87K22 FAMILY 3.6 Internal Oscillator Block The PIC18F87K22 family of devices includes an internal oscillator block which generates two different clock signals. Either clock can be used as the microcontroller’s clock source, which may eliminate the need for an external oscillator circuit on the OSC1 and/or OSC2 pins. ...
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... Reference Clock Output or tempera addition to the F oscillator modes, the device clock in the PIC18F87K22 family can also be configured to provide a reference clock output signal to a port pin. This feature is avail- able in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application ...
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... PIC18F87K22 FAMILY REGISTER 3-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 ROON — ROSSLP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ROON: Reference Oscillator Output Enable bit 1 = Reference oscillator output is available on REFO pin 0 = Reference oscillator output is disabled bit 6 Unimplemented: Read as ‘ ...
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... Real-Time Clock (RTC). Other features may be operat- ing that do not require a device clock source (i.e., MSSP slave, INTx pins and others). Peripherals that may add significant current consumption are listed in Section 31.2 “DC Characteristics: Power-Down and Supply Current PIC18F87K22 Family (Industrial/ Extended)”. and 3.9 Power-up Delays ...
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... PIC18F87K22 FAMILY NOTES: DS39960D-page 56 2009-2011 Microchip Technology Inc. ...
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... POWER-MANAGED MODES The PIC18F87K22 family of devices offers a total of seven operating modes for more efficient power man- agement. These modes provide a variety of options for selective power conservation in applications where resources may be limited (such as battery-powered devices). There are three categories of power-managed mode: • ...
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... PIC18F87K22 FAMILY 4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This for- mula assumes that the new clock source is stable. ...
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... TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 SOSC OSC1 T PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS<1:0> bits Changed Note 1024 OST OSC PLL 2: Clock transition typically occurs within 2-4 T 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY n-1 n (1) Clock Transition OSC OST (1) PLL ( n-1 n ...
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... PIC18F87K22 FAMILY 4.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer. In this mode, the primary clock is shut down. When using the LF-INTOSC source, this mode provides the best power conservation of all the Run modes, while still executing code ...
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... OST OSC PLL 2: Clock transition typically occurs within 2-4 T 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY On transitions from RC_RUN mode to PRI_RUN mode, (Parameter 39, the device continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the ...
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... PIC18F87K22 FAMILY 4.3 Sleep Mode The power-managed Sleep mode in the PIC18F87K22 family of devices is identical to the legacy Sleep mode offered in all other PIC devices entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the ...
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... Peripheral Clock Program Counter Wake Event 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY 4.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the SOSC oscillator. This mode is entered from SEC_RUN by set- ting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set the IDLEN bit first, then set the SCS< ...
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... Many peripheral modules have a corresponding PMD bit. There are four PMD registers in the PIC18F87K22 family devices: PMD0, PMD1, PMD2 and PMD3. These registers have bits associated with each module for disabling or enabling a particular peripheral ...
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... TMR12MD: TMR12MD Disable bit 1 = PMD is enabled and all TMR12MD clock sources are disabled 0 = PMD is disabled and TMR12MD is enabled Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22). Note 1: 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-0 R/W-0 R/W-0 CCP7MD CCP6MD CCP5MD U = Unimplemented bit, read as ‘ ...
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... PIC18F87K22 FAMILY REGISTER 4-2: PMD2: PERIPHERAL MODULE DISABLE REGISTER 2 R/W-0 R/W-0 R/W-0 (1) TMR10MD TMR8MD TMR7MD bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 TMR10MD: TMR10MD Disable bit 1 = Peripheral Module Disable (PMD) is enabled and all TMR10MD clock sources are disabled ...
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... PMD is enabled for EMB, disabling all of its clock sources 0 = PMD is disabled for EMB RTCCMD can only be set to ‘1’ after an EECON2 unlock sequence. Refer to Note 1: Clock and Calendar (RTCC)” 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-0 R/W-0 R/W-0 (1) TMR4MD ...
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... PIC18F87K22 FAMILY REGISTER 4-4: PMD0: PERIPHERAL MODULE DISABLE REGISTER 0 R/W-0 R/W-0 R/W-0 CCP3MD CCP2MD CCP1MD bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 CCP3MD: PMD ECCP3 Enable/Disable bit 1 = Peripheral Module Disable (PMD) is enabled for ECCP3, disabling all of its clock sources ...
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... Fail-Safe Clock Monitor is enabled) and modifies the IRCF bits in the OSCCON register (if the internal oscillator block is the device clock source). 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY 4.6.3 EXIT BY RESET Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock becomes ready ...
Page 70
... PIC18F87K22 FAMILY 4.7 Ultra Low-Power Wake-up The Ultra Low-Power Wake-up (ULPWU) on pin, RA0, allows a slow falling voltage to generate an interrupt without excess current consumption. To use this feature: 1. Charge the capacitor on RA0 by configuring the RA0 pin to an output and setting it to ‘1’. ...
Page 71
... OST (Parameter F12, Table 31-7 also designated as T Execution continues during T 4: The clock source is dependent upon the settings of the SCS (OSCCON<1:0>), IRCF (OSCCON<6:4>) 5: and FOSC (CONFIG1H<3:0>) bits. 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY (5) Exit Delay LP, XT, HS HSPLL EC CSD (2) (2) ...
Page 72
... PIC18F87K22 FAMILY NOTES: DS39960D-page 72 2009-2011 Microchip Technology Inc. ...
Page 73
... RESET The PIC18F87K22 family of devices differentiates between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Configuration Mismatch (CM) Reset f) Brown-out Reset (BOR) g) RESET Instruction h) Stack Full Reset ...
Page 74
... PIC18F87K22 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1 R/W-1 IPEN SBOREN CM bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) ...
Page 75
... To capture multiple events, the user manually resets the bit to ‘1’ in software following any Power-on Reset. 5.4 Brown-out Reset (BOR) The PIC18F87K22 family has four BOR Power modes: • High-Power BOR • Medium Power BOR • Low-Power BOR • Zero-Power BOR Each power Mode is selected by the BORPWR< ...
Page 76
... PWRTEN bit (CONFIG2L<0>). The main function is to ensure that the device voltage is stable before code is executed. The Power-up Timer (PWRT) of the PIC18F87K22 family devices is a 13-bit counter that uses the LF-INTOSC source as the clock input. This yields an approximate time interval of 2,048 x 32 ms. ...
Page 77
... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY T PWRT T PWRT , V RISE > 3. PWRT ): CASE 1 DD ...
Page 78
... PIC18F87K22 FAMILY 5.7 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...
Page 79
... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: See Table 5-1 for Reset value for specific condition. 4: 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset Stack Resets, CM Resets ...
Page 80
... PIC18F87K22 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices INDF2 PIC18F6XK22 PIC18F8XK22 POSTINC2 PIC18F6XK22 PIC18F8XK22 POSTDEC2 PIC18F6XK22 PIC18F8XK22 PREINC2 PIC18F6XK22 PIC18F8XK22 PLUSW2 PIC18F6XK22 PIC18F8XK22 FSR2H PIC18F6XK22 PIC18F8XK22 FSR2L PIC18F6XK22 PIC18F8XK22 STATUS PIC18F6XK22 PIC18F8XK22 TMR0H PIC18F6XK22 PIC18F8XK22 TMR0L ...
Page 81
... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: See Table 5-1 for Reset value for specific condition. 4: 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset Stack Resets, CM Resets ...
Page 82
... PIC18F87K22 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices IPR3 PIC18F6XK22 PIC18F8XK22 PIR3 PIC18F6XK22 PIC18F8XK22 PIE3 PIC18F6XK22 PIC18F8XK22 IPR2 PIC18F6XK22 PIC18F8XK22 PIR2 PIC18F6XK22 PIC18F8XK22 PIE2 PIC18F6XK22 PIC18F8XK22 IPR1 PIC18F6XK22 PIC18F8XK22 PIR1 PIC18F6XK22 PIC18F8XK22 PIE1 PIC18F6XK22 PIC18F8XK22 PSTR1CON ...
Page 83
... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: See Table 5-1 for Reset value for specific condition. 4: 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset Stack Resets, CM Resets ...
Page 84
... PIC18F87K22 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices RTCCFG PIC18F6XK22 PIC18F8XK22 RTCCAL PIC18F6XK22 PIC18F8XK22 RTCVALH PIC18F6XK22 PIC18F8XK22 RTCVALL PIC18F6XK22 PIC18F8XK22 ALRMCFG PIC18F6XK22 PIC18F8XK22 ALRMRPT PIC18F6XK22 PIC18F8XK22 ALRMVALH PIC18F6XK22 PIC18F8XK22 ALRMVALL PIC18F6XK22 PIC18F8XK22 CTMUCONH PIC18F6XK22 PIC18F8XK22 CTMUCONL ...
Page 85
... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: See Table 5-1 for Reset value for specific condition. 4: 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset Stack Resets, CM Resets ...
Page 86
... PIC18F87K22 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices PIC18F66K22 PIC18F86K22 ODCON2 PIC18F67K22 PIC18F87K22 ODCON2 PIC18F65K22 PIC18F85K22 ODCON3 PIC18F6XK22 PIC18F8XK22 MEMCON PIC18F6XK22 PIC18F8XK22 ANCON0 PIC18F6XK22 PIC18F8XK22 ANCON1 PIC18F6XK22 PIC18F8XK22 ANCON2 PIC18F6XK22 PIC18F8XK22 RCSTA2 PIC18F6XK22 PIC18F8XK22 TXSTA2 PIC18F6XK22 PIC18F8XK22 ...
Page 87
... MEMORY ORGANIZATION PIC18F87K22 family devices have these types of memory: • Program Memory • Data RAM • Data EEPROM As Harvard architecture devices, the data and program memories use separate busses. concurrent access of the two memory spaces. FIGURE 6-1: MEMORY MAPS FOR PIC18F87K22 FAMILY DEVICES ...
Page 88
... Flash memory, storing up to 16,384 single-word instructions • PIC18F66K22 and PIC18F86K22 – 64 Kbytes of Flash memory, storing up to 32,768 single-word instructions • PIC18F67K22 and PIC18F87K22 – 128 Kbytes of Flash memory, storing up to 65,536 single-word instructions The program memory maps for individual family members are shown in Figure 6-1 ...
Page 89
... Microchip Technology Inc. PIC18F87K22 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers ...
Page 90
... PIC18F87K22 FAMILY 6.1.3.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 6-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack ...
Page 91
... SUB1 RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY 6.1.5 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
Page 92
... PIC18F87K22 FAMILY 6.2 PIC18 Instruction Cycle 6.2.1 CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping, quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the Program Counter is incremented on every Q1, with the instruction fetched from the program memory and latched into the Instruction Register (IR) during Q4 ...
Page 93
... ADDWF 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
Page 94
... PIC18F87K22 FAMILY 6.3 Data Memory Organization The operation of some aspects of data Note: memory are changed when the PIC18 extended instruction set is enabled. See Section 6.6 “Data Memory and the Extended Instruction Set” information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4,096 bytes of data memory ...
Page 95
... BSR value, to access these registers. 2: These addresses are unused for devices with 32 Kbytes of program memory (PIC18FX5K22). For those devices, read these addresses at 00h. 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY Data Memory Map 000h Access RAM ...
Page 96
... PIC18F87K22 FAMILY FIGURE 6-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) (1) BSR (2) Bank Select The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) Note 1: to the registers of the Access Bank. The MOVFF instruction embeds the entire 12-bit address in the instruction. ...
Page 97
... RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy all of Bank 15 (F00h to FFFh) and the top part of Bank 14 (EF4h to EFFh). A list of these registers is given in Table 6-2. TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F87K22 FAMILY Name Name Addr. Addr. (1) FFFh TOSU ...
Page 98
... PIC18F87K22 FAMILY TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F87K22 FAMILY (CONTINUED) Name Name Addr. Addr. (3) (3) F3Fh TMR7H F32h TMR12 (3) (3) F3Eh TMR7L F31h PR12 (3) (3) F3Dh T7CON F30h T12CON (3) F3Ch T7GCON F2Fh CM2CON F3Bh TMR6 F2Eh CM3CON F3Ah PR6 ...
Page 99
... TABLE 6-2: PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED) Address File Name Bit 7 Bit 6 FE6h POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) FE5h POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) ...
Page 100
... PIC18F87K22 FAMILY TABLE 6-2: PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED) Address File Name Bit 7 Bit 6 FB6h PIE4 CCP10IE (3) CCP9IE FB5h CVRCON CVREN CVROE FB4h CMSTAT CMP3OUT CMP2OUT FB3h TMR3H Timer3 Register High Byte FB2h TMR3L Timer3 Register Low Byte FB1h T3CON ...
Page 101
... TABLE 6-2: PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED) Address File Name Bit 7 Bit 6 F86h PORTG — — F85h PORTF RF7 RF6 F84h PORTE RE7 RE6 F83h PORTD RD7 RD6 F82h PORTC RC7 RC6 F81h PORTB RB7 RB6 F80h PORTA RA7 RA6 ...
Page 102
... PIC18F87K22 FAMILY TABLE 6-2: PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED) Address File Name Bit 7 Bit 6 F5Ch RTCVALL RTCC Value Low Register Window Based on RTCPTR<1:0> F5Bh ALRMCFG ALRMEN CHIME F5Ah ALRMRPT ARPT7 ARPT6 F59h ALRMVALH Alarm Value High Register Window Based on APTR<1:0> ...
Page 103
... TABLE 6-2: PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED) Address File Name Bit 7 Bit 6 F2Ch CCPTMRS1 C7TSEL1 C7TSEL0 F2Bh CCPTMRS2 — — F2Ah REFOCON ROON — F29h ODCON1 SSP1OD CCP2OD F28h ODCON2 CCP10OD (3) CCP9OD F27h ODCON3 U2OD U1OD (2) F26h MEMCON EBDIS — ...
Page 104
... PIC18F87K22 FAMILY 6.3.5 STATUS REGISTER The STATUS register, shown in Register the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC bits, the write to these five bits is disabled. ...
Page 105
... Least Significant Byte. This address specifies the instruction’s data source as either a register address in one of the banks 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY of data RAM (see Section 6.3.3 “General Purpose File” location in the Access Bank (see Register Section 6.3.2 “ ...
Page 106
... PIC18F87K22 FAMILY 6.4.3.1 FSR Registers and the INDF Operand At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers: FSRnH and FSRnL. The four upper bits of the FSRnH register are not used, so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion ...
Page 107
... In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY 6.4.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations ...
Page 108
... PIC18F87K22 FAMILY 6.6 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Using the Access Bank for many of the core PIC18 instructions introduces a new addressing mode for the data memory space ...
Page 109
... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY 000h 060h Bank 0 100h Bank 1 through Bank 14 F00h ...
Page 110
... PIC18F87K22 FAMILY 6.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user-defined “ ...
Page 111
... Program Memory (TBLPTR) Note 1: The Table Pointer register points to a byte in program memory. 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY 7.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 112
... PIC18F87K22 FAMILY FIGURE 7-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: The Table Pointer actually points to one of 64 holding registers; the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 “ ...
Page 113
... The RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error Note 1: condition. 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-0 R/W-x R/W-0 (1) FREE ...
Page 114
... PIC18F87K22 FAMILY 7.2.2 TABLAT – TABLE LATCH REGISTER The Table Latch (TABLAT eight-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 7.2.3 TBLPTR – TABLE POINTER ...
Page 115
... MOVF TABLAT, W MOVF WORD_ODD 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, the TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 116
... PIC18F87K22 FAMILY 7.4 Erasing Flash Program Memory The erase blocks are: • PIC18FX5K22 and PIC18FX6K22 – 32 words or 64 bytes • PIC18FX7K22 – 64 words or 128 bytes Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block 128 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR< ...
Page 117
... TBLPTR = xxxxx0 TBLPTR = xxxxx1 Holding Register 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write is terminated by the internal programming timer. The EEPROM on-chip timer controls the write time. ...
Page 118
... PIC18F87K22 FAMILY 7.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location should be: 1. Read the 64 or 128 bytes into RAM. 2. Update the data values in RAM as necessary. 3. Load the Table Pointer register with the address being erased. ...
Page 119
... POSTINC0, WREG MOVWF TABLAT TBLWT+* DECFSZ COUNTER BRA WRITE_BYTE_TO_HREGS 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY ; number of bytes in erase block ; point to buffer ; Load TBLPTR with the base ; address of the memory block ; read into TABLAT, and inc ; get data ; store data ; done? ...
Page 120
... PIC18F87K22 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BSF EECON1, EEPGD BCF EECON1, CFGS BSF EECON1, WREN BCF INTCON, GIE MOVLW 0x55 Required MOVWF EECON2 Sequence MOVLW 0xAA MOVWF EECON2 BSF EECON1, WR BSF INTCON, GIE BCF EECON1, WREN 7.5.2 ...
Page 121
... The External Memory Bus (EMB) allows the device to access external memory devices (such as Flash, EPROM or SRAM) as program or data memory. It supports both 8 and 16-Bit Data Width modes and three address widths bits. TABLE 8-1: PIC18F87K22 FAMILY EXTERNAL BUS – I/O PORT FUNCTIONS Name Port RD0/AD0 PORTD RD1/AD1 ...
Page 122
... PIC18F87K22 FAMILY 8.1 External Memory Bus Control The operation of the interface is controlled by the MEMCON register (Register 8-1). This register is available in all program memory operating modes except Microcontroller mode. In this mode, the register is disabled and cannot be written to. The EBDIS bit (MEMCON<7>) controls the operation of the bus and related port functions ...
Page 123
... Address and Data Width The PIC18F87K22 family of devices can be indepen- dently configured for different address and data widths on the same memory bus. Both address and data width are set by Configuration bits in the CONFIG3L register. As Configuration bits, this means that these options can only be configured by programming the device and are not controllable in software ...
Page 124
... Program Memory Modes and the External Memory Bus The PIC18F87K22 family of devices is capable of operating in one of two program memory modes, using combinations of on-chip and external program memory. The functions of the multiplexed port pins depend on the program memory mode selected, as well as the setting of the EBDIS bit ...
Page 125
... BYTE WRITE MODE Figure 8-1 shows an example of 16-Bit Byte Write mode for PIC18F87K22 family devices. This mode is used for two separate 8-bit memories connected for 16-bit operation. This generally includes basic EPROM and Flash devices. It allows table writes to byte-wide external memories ...
Page 126
... WORD WRITE MODE Figure 8-2 shows an example of 16-Bit Word Write mode for PIC18F87K22 family devices. This mode is used for word-wide memories, which includes some of the EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory, and table writes to any type of word-wide external memories ...
Page 127
... Demultiplexing is only required when multiple memory devices are accessed. 3: 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’s BYTE/WORD pin to provide the select signal ...
Page 128
... PIC18F87K22 FAMILY 8.6.4 16-BIT MODE TIMING The presentation of control signals on the External Memory Bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 8-4 and Figure 8-5. FIGURE 8-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) ...
Page 129
... This signal only applies to table writes. See 2: 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the second byte will be enabled to form the 16-bit instruc- tion word ...
Page 130
... PIC18F87K22 FAMILY 8.7.1 8-BIT MODE TIMING The presentation of control signals on the External Memory Bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 8-7 and Figure 8-8. FIGURE 8-7: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) ...
Page 131
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during External Memory Bus access. Unimplemented in 64-pin devices (PIC18F6XK22), read as ‘0’. Note 1: 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY In Sleep and Idle modes, the microcontroller core does not need to access data; bus operations are suspended. The state of the external bus is frozen, with ...
Page 132
... PIC18F87K22 FAMILY NOTES: DS39960D-page 132 2009-2011 Microchip Technology Inc. ...
Page 133
... EEADRH holds the two MSbs of the address; the upper 6 bits are ignored. The 10-bit range of the pair can address a memory range of 1024 bytes (00h to 3FFh). 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY 9.2 EECON1 and EECON2 Registers Access to the data EEPROM is controlled by two registers: EECON1 and EECON2 ...
Page 134
... PIC18F87K22 FAMILY REGISTER 9-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 EEPGD CFGS — bit Settable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory ...
Page 135
... EEPROM. The WREN bit is not cleared by hardware. 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY After a write sequence has been initiated, EECON1, EEADRH:EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set ...
Page 136
... PIC18F87K22 FAMILY EXAMPLE 9-1: DATA EEPROM READ MOVLW DATA_EE_ADDRH MOVWF EEADRH MOVLW DATA_EE_ADDR MOVWF EEADR BCF EECON1, EEPGD BCF EECON1, CFGS BSF EECON1, RD NOP MOVF EEDATA, W EXAMPLE 9-2: DATA EEPROM WRITE MOVLW DATA_EE_ADDRH MOVWF EEADRH MOVLW DATA_EE_ADDR MOVWF EEADR MOVLW DATA_EE_DATA ...
Page 137
... BRA LOOP BCF EECON1, WREN BSF INTCON, GIE 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY 9.8 Using the Data EEPROM The data EEPROM is a high-endurance, byte address- able array that has been optimized for the storage of frequently changing variables or other data that is updated often). ...
Page 138
... PIC18F87K22 FAMILY TABLE 9-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL EEADRH EEPROM Address Register High Byte EEADR EEPROM Address Register Low Byte EEDATA EEPROM Data Register EECON2 EEPROM Control Register 2 (not a physical register) EECON1 EEPGD ...
Page 139
... Hardware Multiply Without Hardware Multiply Signed Hardware Multiply Without Hardware Multiply Unsigned Hardware Multiply Without Hardware Multiply Signed Hardware Multiply 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY EXAMPLE 10-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 10-2: MOVF ARG1, W MULWF ARG2 BTFSC ARG2, SB ...
Page 140
... PIC18F87K22 FAMILY Example 10-3 shows the sequence unsigned multiplication. Equation 10-1 algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 10- UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L ARG2H:ARG2L RES3:RES0 = 16 (ARG1H ARG2H (ARG1H ARG2L (ARG1L ARG2H 2 (ARG1L ...
Page 141
... INTERRUPTS Members of the PIC18F87K22 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress ...
Page 142
... PIC18F87K22 FAMILY FIGURE 11-1: PIC18F87K22 FAMILY INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7,5:0> PIE2<7,5:0> IPR2<7,5:0> PIR3<7,5> PIE3<7,5> IPR3<7,5> PIR4<7:0> PIE4<7:0> IPR4<7:0> PIR5<7:0> PIE5<7:0> IPR5<7:0> PIR6<4, 2:0> PIE6<4, 2:0> IPR6<4, 2:0> High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7, 5:0> PIE2<7, 5:0> ...
Page 143
... A mismatch condition will continue to set this bit. Reading PORTB, and then waiting one additional instruction Note 1: cycle, will end the mismatch condition and allow the bit to be cleared. 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY Interrupt flag bits are set when an interrupt Note: condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit ...
Page 144
... PIC18F87K22 FAMILY REGISTER 11-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual TRIS register values ...
Page 145
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding Note: enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-0 R/W-0 R/W-0 INT2IE ...
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... PIC18F87K22 FAMILY 11.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are six Peripheral Interrupt Request (Flag) registers (PIR1 through PIR6). REGISTER 11-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
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... TMR3 register overflowed (must be cleared in software TMR3 register did not overflow bit 0 TMR3GIF: TMR3 Gate Interrupt Flag bit 1 = Timer gate interrupt occurred (must be cleared in software timer gate interrupt occurred 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-0 R/W-0 R/W-0 BCL2IF BCL1IF HLVDIF U = Unimplemented bit, read as ‘ ...
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... PIC18F87K22 FAMILY REGISTER 11-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 U-0 R-0 TMR5GIF — RC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 TMR5GIF: Timer5 Gate Interrupt Flag bit 1 = Timer gate interrupt occurred (must be cleared in software) ...
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... A TMR register compare match occurred (must be cleared in software TMR register compare match occurred PWM Mode: Not used in PWM mode. Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22). Note 1: 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-0 R/W-0 R/W-0 CCP7IF CCP6IF CCP5IF U = Unimplemented bit, read as ‘ ...
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... PIC18F87K22 FAMILY REGISTER 11-8: PIR5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 5 R/W-0 R/W-0 R/W-0 (1) (1) TMR7GIF TMR12IF TMR10IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 TMR7GIF: TMR7 Gate Interrupt Flag bits 1 = TMR gate interrupt occurred (bit must be cleared in software) ...
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... CMP2 interrupt occurred (must be cleared in software CMP2 interrupt occurred bit 0 CMP1IF: CM1 Interrupt Flag bit 1 = CMP1 interrupt occurred (must be cleared in software CMP1 interrupt occurred 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-0 U-0 R/W-0 EEIF — CMP3IF U = Unimplemented bit, read as ‘0’ ...
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... PIC18F87K22 FAMILY 11.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are six Peripheral Interrupt Enable registers (PIE1 through PIE6). When IPEN (RCON<7> the PEIE bit must be set to enable any of these peripheral interrupts ...
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... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 TMR3GIE: Timer3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-0 R/W-0 R/W-0 BCL2IE BCL1IE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 ...
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... PIC18F87K22 FAMILY REGISTER 11-12: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 U-0 R-0 TMR5GIE — RC2IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 TMR5GIE: Timer5 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 Unimplemented: Read as ‘0’ ...
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... TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enables the TMR4 to PR4 match interrupt 0 = Disables the TMR4 to PR4 match interrupt Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22). Note 1: 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-0 R/W-0 R/W-0 (1) (1) TMR8IE ...
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... PIC18F87K22 FAMILY REGISTER 11-15: PIE6: PERIPHERAL INTERRUPT ENABLE REGISTER 6 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4 EEIE: Data EEDATA/Flash Write Operation Enable bit ...
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... TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-1 R/W-1 R/W-1 TX1IP SSP1IP TMR1GIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC18F87K22 FAMILY REGISTER 11-17: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 U-0 R/W-1 OSCFIP — SSP2IP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 Unimplemented: Read as ‘0’ ...
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... Bit is set bit 7-0 CCP<10:3>IP: CCP<10:3> Interrupt Priority bits 1 = High priority 0 = Low priority Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22). Note 1: 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY R-1 R/W-1 R/W-1 TX2IP CTMUIP CCP2IP U = Unimplemented bit, read as ‘0’ ...
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... PIC18F87K22 FAMILY REGISTER 11-20: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5 R/W-1 R/W-1 R/W-1 (1) (1) TMR7GIP TMR12IP TMR10IP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 TMR7GIP: TMR7 Gate Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 TMR12IP: TMR12 to PR12 Match Interrupt Priority bit ...
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... CMP2IP: CMP2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CMP1IP: CMP1 Interrupt Priority bit 1 = High priority 0 = Low priority 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-1 U-0 R/W-1 EEIP — CMP3IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC18F87K22 FAMILY 11.5 RCON Register The RCON register contains the bits used to determine the cause of the last Reset, or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 11-22: RCON: RESET CONTROL REGISTER R/W-0 R/W-1 ...
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... BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY 11.7 TMR0 Interrupt In 8-bit mode (the default), an overflow in the TMR0 register (FFh 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh 0000h) will set TMR0IF. ...
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... PIC18F87K22 FAMILY TABLE 11-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL INTCON2 RBPU INTEDG0 INTCON3 INT2IP INT1IP PIR1 PSPIP ADIF PIR2 OSCFIF — PIR3 TMR5GIF — (1) (1) PIR4 CCP10IF CCP9IF (1) (1) PIR5 TMR7GIF TMR12IF PIR6 — — ...
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... RD TRIS PORT 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY 12.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V All of the digital ports are 5.5V input tolerant. The ana- log ports have the same tolerance – ...
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... PIC18F87K22 FAMILY REGISTER 12-1: PADCFG1: PAD CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 (2) RDPU REPU RJPU bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RDPU: PORTD Pull-up Enable bit 1 = PORTD pull-up resistors are enabled by individual port latch values ...
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... Open-drain capability is disabled bit 4-1 Unimplemented: Read as ‘0’ bit 0 SSP2OD: MSSP2 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY FIGURE 12-2: USING THE OPEN-DRAIN OUTPUT (USART SHOWN AS EXAMPLE) 3.3V PIC18F87K22 (at logic ‘ ...
Page 168
... PIC18F87K22 FAMILY REGISTER 12-3: ODCON2: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 (1) (1) CCP10OD CCP9OD CCP8OD bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 CCP10OD: CCP10 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled ...
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... ANALOG AND DIGITAL PORTS Many of the ports multiplex analog and digital function- ality, providing a lot of flexibility for hardware designers. PIC18F87K22 family devices can make any analog pin analog or digital, depending on an application’s needs. The ports’ analog/digital functionality is controlled by registers: ANCON0, ANCON1 and ANCON2. ...
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... PIC18F87K22 FAMILY 12.2 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corre- sponding Data Direction and Output Latch registers are TRISA and LATA. RA4/T0CKI is a Schmitt Trigger input. All other PORTA pins have TTL input levels and full CMOS output drivers. RA5 and RA< ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, Note 1: they are disabled and read as ‘x’. 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY I/O I/O Type O DIG LATA< ...
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... PIC18F87K22 FAMILY 12.3 PORTB, TRISB and LATB Registers PORTB is an eight-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISB and LATB. All pins on PORTB are digital only. EXAMPLE 12-2: INITIALIZING PORTB CLRF PORTB ; Initialize PORTB by ; clearing output ...
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... PEIE/GIEL INTCON2 RBPU INTEDG0 INTCON3 INT2IP INT1IP ODCON1 SSP1OD CCP2OD Legend: Shaded cells are not used by PORTB. 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY I/O I/O Type O DIG LATB<3> data output. I TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared External Interrupt 3 input ...
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... PIC18F87K22 FAMILY 12.4 PORTC, TRISC and LATC Registers PORTC is an eight-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISC and LATC. Only PORTC pins, RC2 through RC7, are digital only pins. PORTC is multiplexed with ECCP, MSSP and EUSART ...
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... TRISC6 ODCON1 SSP1OD CCP2OD ODCON3 U2OD U1OD Legend: Shaded cells are not used by PORTC. 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY I/O Description Type DIG LATC<3> data output. ST PORTC<3> data input. DIG SPI clock output (MSSP module); takes priority over port data. ...
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... PIC18F87K22 FAMILY 12.5 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISD and LATD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. ...
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... TRISD7 TRISD6 PADCFG1 RDPU REPU ODCON1 SSP1OD CCP2OD Legend: Shaded cells are not used by PORTD. Unimplemented on PIC18F6XK22 devices, read as ‘0’. Note 1: 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY I/O I/O Type O DIG LATD<3> data output PORTD<3> data input. I/O TTL Parallel Slave Port data ...
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... PIC18F87K22 FAMILY 12.6 PORTE, TRISE and LATE Registers PORTE is an eight-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISE and LATE. All pins on PORTE are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. The RE7 pin is also configurable for open-drain output when ECCP2 is active on this pin ...
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... Don’t care (TRIS bit does not affect port direction or is overridden for this option). Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared and in Microcontroller mode. Note 1: This feature is only available on PIC18F8XKXX devices. 2: 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY I/O I/O Type O DIG LATE< ...
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... PIC18F87K22 FAMILY TABLE 12-9: PORTE FUNCTIONS (CONTINUED) TRIS Pin Name Function Setting RE7/ECCP2/ RE7 0 P2A/AD15 1 (1) ECCP2 0 1 P2A 0 (2) AD15 Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, Legend Don’t care (TRIS bit does not affect port direction or is overridden for this option). ...
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... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, Legend: TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY EXAMPLE 12-6: CLRF PORTF ...
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... PIC18F87K22 FAMILY TABLE 12-11: PORTF FUNCTIONS (CONTINUED) TRIS Pin Name Function Setting RF6/AN11/C1INA RF6 0 1 AN11 1 C1INA 1 RF7/AN5/SS1 RF7 0 1 AN5 1 SS1 Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, Legend: TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). ...
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... Legend Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTG pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input ...
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... PIC18F87K22 FAMILY TABLE 12-13: PORTG FUNCTIONS (CONTINUED) TRIS Pin Name Function Setting RG2/RX2/DT2/ RG2 0 AN18/C3INA 1 RX2 1 DT2 1 1 AN18 1 C3INA x RG3/CCP4/AN17/ RG3 0 P3D/C3INB 1 CCP4 0 1 AN17 1 P3D 0 C3INB x RG4/RTCC/ RG4 0 T7CKI/T5G/ 1 CCP5/AN16/ RTCC x P1D/C3INC T7CKI x T5G x CCP5 0 1 AN16 1 P1D 0 C3INC ...
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... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, Legend Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY EXAMPLE 12-8: CLRF PORTH CLRF LATH ...
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... PIC18F87K22 FAMILY TABLE 12-15: PORTH FUNCTIONS (CONTINUED) TRIS Pin Name Function Setting RH4/CCP9/ RH4 0 P3C/AN12/ 1 C2INC CCP9 0 1 P3C 0 AN12 1 C2INC x RH5/CCP8/ RH5 0 P3B/AN13/ 1 C2IND CCP8 0 1 P3B 0 AN13 1 C2IND x RH6/CCP7/ RH6 0 P1C/AN14/ 1 C1INC CCP7 0 1 P1C 0 AN14 1 C1INC x RH7/CCP6/ RH7 ...
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... PORTJ pins function as control outputs for the inter- face. This occurs automatically when the interface is enabled by clearing the EBDIS (MEMCON<7>). The TRISJ bits are also overridden. 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY Bit 5 Bit 4 Bit 3 RH5 RH4 RH3 LATH5 LATH4 ...
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... PIC18F87K22 FAMILY TABLE 12-17: PORTJ FUNCTIONS TRIS Pin Name Function Setting RJ0/ALE RJ0 0 1 ALE x RJ1/OE RJ1 RJ2/WRL RJ2 0 1 WRL x RJ3/WRH RJ3 0 1 WRH x RJ4/BA0 RJ4 0 1 BA0 x RJ5/CE RJ5 RJ6/LB RJ6 RJ7/UB RJ7 Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, Legend Don’ ...
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... OBF bits can be polled and the appropriate action taken. The timing for the control signals in Write and Read modes is shown in Figure 12-4 and respectively. 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY FIGURE 12-3: Data Bus WR LATD or PORTD Data Latch Q RD PORTD ...
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... PIC18F87K22 FAMILY REGISTER 12-5: PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER R-0 R-0 R/W-0 IBF OBF IBOV bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IBF: Input Buffer Full Status bit word has been received and is waiting to be read by the CPU ...
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... PSPIF ADIF PIE1 PSPIE ADIE IPR1 PSPIP ADIP PMD1 PSPMD CTMUMD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY Bit 5 Bit 4 Bit 3 RD5 RD4 RD3 LATD5 LATD4 ...
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... PIC18F87K22 FAMILY NOTES: DS39960D-page 192 2009-2011 Microchip Technology Inc. ...
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... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY The T0CON register aspects of the module’s operation, including the prescale selection both readable and writable. Figure 13-1 provides a simplified block diagram of the Timer0 module in 8-bit mode. ...
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... PIC18F87K22 FAMILY 13.1 Timer0 Operation Timer0 can operate as either a timer or a counter. The mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see “Prescaler”). If the Section 13.3 TMR0 register is written to, the increment is inhibited for the following two instruction cycles ...
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... PEIE/GIEL T0CON TMR0ON T08BIT Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY 13.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...
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... PIC18F87K22 FAMILY NOTES: DS39960D-page 196 2009-2011 Microchip Technology Inc. ...
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... The F clock source should not be selected if the timer will be used with the ECCP capture/compare features. Note 1: OSC 2009-2011 Microchip Technology Inc. PIC18F87K22 FAMILY Figure 14-1 displays a simplified block diagram of the Timer1 module. The Timer1 oscillator can also be used as a low-power clock source for the microcontroller in power-managed operation ...
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... PIC18F87K22 FAMILY 14.1 Timer1 Gate Control Register The Timer1 Gate Control register displayed in Register 14-2, is used to control the Timer1 gate. REGISTER 14-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0 R/W-0 R/W-0 TMR1GE T1GPOL T1GTM bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘ ...
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... Microchip Technology Inc. PIC18F87K22 FAMILY 14.3.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. When enabled to count, Timer1 is incremented on the rising edge of the external clock input, T1CKI. Either of these external clock sources can be synchronized to the ...
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... PIC18F87K22 FAMILY FIGURE 14-1: TIMER1 BLOCK DIAGRAM T1GSS<1:0> T1G 00 From TMR2 01 Match PR2 From Comparator 1 10 Output From Comparator 2 11 Output TMR1ON T1GPOL T1GTM Set Flag bit, TMR1IF, on Overflow TMR1 TMR1H SOSCO/SCLKI OUT SOSC SOSCI EN T1CON.SOSCEN T3CON.SOSCEN SOSCGO SCS<1:0> T1CKI ST Buffer is a high-speed type when using T1CKI. ...