PIC18F96J60T-I/PF Microchip Technology, PIC18F96J60T-I/PF Datasheet - Page 16

• Manufacturer Part Number: PIC18F96J60T-I/PF
• Description: 64KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J60T-I/PF

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164333 - MODULE SKT FOR PM3 100QFPAC162064 - HEADER INTFC MPLABICD2 64/80/100
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F97J60 FAMILY
5.0
The Configuration Words of the PIC18F97J60 family
devices are implemented as volatile memory registers,
as opposed to the programmable nonvolatile memory
used in other PIC18 devices. All of the Configuration
registers
CONFIG2H,
automatically loaded following each device Reset.
The data for these registers is taken from the four Flash
Configuration Words located at the end of program
memory. Configuration data is stored in order, starting
with CONFIG1L in the lowest Flash address and
ending with CONFIG4H in the last address. The
mapping to specific Configuration Words is shown in
Table 5-1. While four words are reserved in program
memory, only three words (CONFIG1L through
CONFIG3H) are used for device configuration. Users
should
Configuration Word data and write their application
code accordingly.
The upper four bits of each Configuration Word should
always be stored in program memory as ‘1111’. This is
done so these program memory addresses will always
be ‘1111 xxxx xxxx xxxx’ and interpreted as a NOP
instruction if they were ever to be executed. Because
the corresponding bits in the Configuration Words are
unimplemented, they will not change the device’s
configuration.
The Configuration and Device ID registers are
summarized in Table 5-2. A listing of the individual
Configuration bits and their options is provided in
Table 5-3.
TABLE 5-2:
DS39688D-page 16
300000h CONFIG1L
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
300004h CONFIG3L
300005h CONFIG3H
3FFFFEh DEVID1
3FFFFFh DEVID2
Legend:
Note 1:
File Name
2:
3:
4:
5:
CONFIGURATION WORD
always
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition.
Shaded cells are unimplemented, read as ‘0’.
The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if
it is accidentally executed.
This bit should always be maintained as ‘0’.
Implemented in 100-pin devices only.
Implemented in 80-pin and 100-pin devices only. This bit should always be maintained as ‘1’ for 64-pin devices.
DEVID registers are read-only and cannot be programmed by the user.
(CONFIG1L,
CONFIG3L
(5)
(5)
CONFIGURATION BITS AND DEVICE IDS
reserve
DEBUG
WAIT
DEV10
DEV2
IESO
Bit 7
—
—
—
(1)
(1)
(1)
CONFIG1H,
(3)
and
these
FCMEN
XINST
DEV1
DEV9
BW
Bit 6
—
—
—
(1)
(1)
(1)
CONFIG3H)
(3)
locations
STVREN
EMB1
DEV0
DEV8
CONFIG2L,
Bit 5
—
—
—
—
(1)
(1)
(1)
(3)
EMB0
are
for
REV4
DEV7
Bit 4
—
—
—
—
—
(1)
(1)
(1)
(3)
EASHFT
WDTPS3
REV3
DEV6
Bit 3
—
TABLE 5-1:
—
—
—
CONFIG1L
CONFIG1H
CONFIG2L
CONFIG2H
CONFIG3L
CONFIG3H
CONFIG4L
CONFIG4H
Note 1:
(2)
Configuration
(3)
Byte
2:
WDTPS2
ETHLED ECCPMX
FOSC2
REV2
DEV5
Bit 2
CP0
—
—
See Table 2-2 for the complete addresses
within code space for specific devices and
memory sizes.
Unimplemented in PIC18F97J60 family
devices.
(2)
(2)
WDTPS1
MAPPING OF THE FLASH
CONFIGURATION WORDS TO
THE CONFIGURATION
REGISTERS
FOSC1
REV1
DEV4
Bit 1
Code Space
—
—
—
Address
XXXFAh
XXXFBh
XXXFCh
XXXFDh
XXXFEh
XXXFFh
XXXF8h
XXXF9h
© 2009 Microchip Technology Inc.
(4)
CCP2MX
WDTPS0
WDTEN
FOSC0
(1)
REV0
DEV3
Bit 0
—
—
(4)
Configuration
Unprogrammed
Register
Address
See Table 5-4
See Table 5-4
300000h
300001h
300002h
300003h
300004h
300005h
300006h
300007h
111- ---1
---- 01--
11-- -111
---- 1111
1111 1---
---- -111
Default/
Value