PIC18F96J60T-I/PT Microchip Technology, PIC18F96J60T-I/PT Datasheet - Page 221

• Manufacturer Part Number: PIC18F96J60T-I/PT
• Description: 64KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 12x12x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J60T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

REGISTER 18-6:
REGISTER 18-7:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-4
bit 3-2
bit 1-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-2
bit 1
bit 0
U-0
U-0
—
—
Unimplemented: Read as ‘0’
DEFER: Defer Transmission Enable bit (applies to half duplex only)
1 = When the medium is occupied, the MAC waits indefinitely for it to become free when attempting to
0 = When the medium is occupied, the MAC aborts the transmission after the excessive deferral limit
Reserved: Maintain as ‘0’
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
Unimplemented: Read as ‘0’
MIISCAN: MII Scan Enable bit
1 = PHY register at MIREGADR is continuously read and the data is placed in the MIRD registers
0 = No MII Management scan operation is in progress
MIIRD: MII Read Enable bit
1 = PHY register at MIREGADR is read once and the data is placed in the MIRD registers
0 = No MII Management read operation is in progress
DEFER
R/W-0
transmit (use this setting for IEE 802.3 compliance)
is reached
U-0
—
MACON4: MAC CONTROL REGISTER 4
MICMD: MII COMMAND REGISTER
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
R/W-0
U-0
r
—
R/W-0
U-0
—
r
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F97J60 FAMILY
U-0
U-0
—
—
U-0
U-0
—
—
x = Bit is unknown
x = Bit is unknown
MIISCAN
R/W-0
R-0
r
DS39762E-page 221
R/W-0
MIIRD
R-0
r
bit 0
bit 0