PIC18F97J60T-I/PF Microchip Technology, PIC18F97J60T-I/PF Datasheet - Page 475

• Manufacturer Part Number: PIC18F97J60T-I/PF
• Description: 128KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60T-I/PF

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Timing Diagrams and Specifications
© 2009 Microchip Technology Inc.
Time-out Sequence on Power-up (MCLR Tied to V
Timer0 and Timer1 External Clock .......................... 439
Transition for Entry to Idle Mode ................................ 54
Transition for Entry to SEC_RUN Mode .................... 51
Transition for Entry to Sleep Mode ............................ 53
Transition for Two-Speed Start-up (INTRC to HSPLL) ..
Transition for Wake From Idle to Run Mode .............. 54
Transition for Wake From Sleep Mode (HSPLL) ....... 53
Transition From RC_RUN Mode to PRI_RUN Mode . 52
Transition From SEC_RUN Mode to PRI_RUN Mode
Transition to RC_RUN Mode ..................................... 52
AC Characteristics
Capture/Compare/PWM Requirements (Including EC-
CLKO and I/O Requirements ........................... 435, 436
EUSARTx Synchronous Receive Requirements ..... 449
EUSARTx Synchronous Transmission Requirements ...
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode Requirements
External Clock Requirements .................................. 433
I
I
Master SSP I
2
2
C Bus Data Requirements
C Bus Start/Stop Bits Requirements
V
359
(HSPLL) ............................................................. 51
Internal RC Accuracy ....................................... 434
CPx Modules) .................................................. 440
449
(Master Mode, CKE = 0) .................................. 441
(Master Mode, CKE = 1) .................................. 442
(Slave Mode, CKE = 0) .................................... 443
(CKE = 1) ......................................................... 444
(Slave Mode) ................................................... 446
(Slave Mode) ................................................... 445
DD
Rise < T
2
C Bus Data Requirements ................ 448
PWRT
) ............................................ 60
DD
,
PIC18F97J60 FAMILY
Top-of-Stack Access .......................................................... 75
TRISE Register
TSTFSZ ........................................................................... 403
Two-Speed Start-up ................................................. 349, 359
Two-Word Instructions
TXSTAx Register
V
V
Voltage Reference Specifications .................................... 430
Voltage Regulator (On-Chip) ........................................... 358
W
Watchdog Timer (WDT) ........................................... 349, 357
WCOL ...................................................... 292, 293, 294, 297
WCOL Status Flag ................................... 292, 293, 294, 297
WWW Address ................................................................ 477
WWW, On-Line Support ...................................................... 9
X
XORLW ........................................................................... 403
XORWF ........................................................................... 404
DDCORE
Master SSP I
Parallel Slave Port Requirements ............................ 440
PLL Clock ................................................................ 434
Program Memory Write Requirements .................... 437
Reset, Watchdog Timer, Oscillator Start-up Timer,
Timer0 and Timer1 External Clock Requirements ... 439
PSPMODE Bit ......................................................... 163
Example Cases ......................................................... 79
BRGH Bit ................................................................. 309
Associated Registers ............................................... 357
Control Register ....................................................... 357
Programming Considerations .................................. 357
/V
Power-up Timer and Brown-out Reset
Requirements .................................................. 438
CAP
Pin .......................................................... 358
2
C Bus Start/Stop Bits Requirements . 447
DS39762E-page 475