PIC18LF25K22-E/ML Microchip Technology, PIC18LF25K22-E/ML Datasheet - Page 134
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PIC18LF25K22-E/ML
Manufacturer Part Number
PIC18LF25K22-E/ML
Description
32KB, Flash, 1536bytes-RAM,8-bit Family,nanoWatt XLP 28 QFN 6x6mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18LF25K22-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18(L)F2X/4XK22
TABLE 10-1:
DS41412D-page 134
RA0/C12IN0-/AN0
RA1/C12IN1-/AN1
RA2/C2IN+/AN2/
DACOUT/V
RA3/C1IN+/AN3/
V
RA4/CCP5/
C1OUT/SRQ/
T0CKI
RA5/C2OUT/
SRNQ/SS1/
HLVDIN/AN4
Legend:
REF
Pin Name
+
REF
AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal;
CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I
with I
-
2
C.
PORTA I/O SUMMARY
Function
DACOUT
C12IN0-
C12IN1-
HLVDIN
C1OUT
C2OUT
C2IN+
C1IN+
SRNQ
V
T0CKI
V
CCP5
SRQ
RA0
RA1
AN0
AN1
RA2
AN2
RA3
AN3
RA4
RA5
SS1
AN4
REF
REF
+
-
Setting
TRIS
0
1
1
1
0
1
1
1
0
1
1
1
x
1
0
1
1
1
1
0
1
0
1
0
0
1
0
1
0
0
1
1
1
ANSEL
Setting
—
—
—
—
—
—
—
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
1
1
1
0
0
0
0
0
1
1
Type
Pin
Preliminary
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Buffer
Type
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
DIG
DIG
DIG
DIG
TTL
DIG
DIG
TTL
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
ST
ST
ST
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input
enabled.
Comparators C1 and C2 inverting input.
Analog input 0.
LATA<1> data output; not affected by analog input.
PORTA<1> data input; disabled when analog input
enabled.
Comparators C1 and C2 inverting input.
Analog input 1.
LATA<2> data output; not affected by analog input; disabled
when DACOUT enabled.
PORTA<2> data input; disabled when analog input
enabled; disabled when DACOUT enabled.
Comparator C2 non-inverting input.
Analog output 2.
DAC Reference output.
A/D reference voltage (low) input.
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input
enabled.
Comparator C1 non-inverting input.
Analog input 3.
A/D reference voltage (high) input.
LATA<4> data output.
PORTA<4> data input; default configuration on POR.
CCP5 Compare output/PWM output, takes priority over
RA4 output.
Capture 5 input/Compare 5 output/ PWM 5 output.
Comparator C1 output.
SR Latch Q output; take priority over CCP 5 output.
Timer0 external clock input.
LATA<5> data output; not affected by analog input.
PORTA<5> data input; disabled when analog input
enabled.
Comparator C2 output.
SR Latch Q output.
SPI slave select input (MSSP1).
High/Low-Voltage Detect input.
A/D input 4.
Description
2010 Microchip Technology Inc.
2
C
TM
=
Schmitt Trigger input
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