PIC18LF4458-I/PT Microchip Technology, PIC18LF4458-I/PT Datasheet - Page 24

• Manufacturer Part Number: PIC18LF4458-I/PT
• Description: 24KB Flash, 2KB RAM, 256 Bytes EEPROM, 35 I/O, USB, 12bit ADC 44 TQFP 10x10x1mm
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4458-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 24KB (12K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2458/2553/4458/4553
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(V
V
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To oper-
ate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
Converter, which generates the result via successive
approximation.
FIGURE 2-1:
DS39887C-page 24
REF
DD
+ and RA2/AN2/V
and V
Note 1:
SS
), or the voltage level on the RA3/AN3/
Converter
12-Bit
A/D
Channels AN5 through AN7 are not available on 28-pin devices.
Reference
Voltage
A/D BLOCK DIAGRAM
REF
-/CV
REF
pins.
V
V
REF
REF
+
-
(Input Voltage)
VCFG1:VCFG0
V
AIN
X
X
1
0
0
1
X
X
V
DD
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D Converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0 register) is
cleared and the A/D Interrupt Flag bit, ADIF, is set. The
block diagram of the A/D module is shown in Figure 2-1.
V
SS
CHS3:CHS0
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
© 2009 Microchip Technology Inc.
AN12
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
(1)
(1)
(1)