PIC18LF8723T-I/PT Microchip Technology, PIC18LF8723T-I/PT Datasheet
PIC18LF8723T-I/PT
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PIC18LF8723T-I/PT Summary of contents
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... Legend Input Output Power Note 1: All power supply (V ) and ground ( See Table 5-1 for more information. © 2009 Microchip Technology Inc. PIC18F872X FAMILY 2.1 Hardware Requirements In High-Voltage ICSP mode, the PIC18F872X family requires two programmable power supplies; one for V and one for MCLR/V DD have a minimum resolution of 0 ...
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... PIC18F6527/6622/6627/6722/6628/6723 FAMILY PIN DIAGRAM 64-Pin TQFP RE1 1 RE0 2 RG0 3 RG1 4 RG2 5 RG3 6 MCLR/V /RG5 PP 7 RG4 RF7 11 RF6 12 RF5 13 RF4 14 RF3 15 RF2 16 DS39643C-page PIC18F6XXX RB0 48 RB1 47 RB2 46 RB3 45 RB4 44 RB5/PGM 43 RB6/PGC RA6 40 RA7 RB7/PGD 37 RC5 36 RC4 35 RC3 34 RC2 © 2009 Microchip Technology Inc. ...
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... RH3 2 RE1 3 RE0 4 RG0 5 RG1 6 RG2 7 RG3 8 MCLR/V /RG5 PP 9 RG4 RF7 13 RF6 14 RF5 15 RF4 16 RF3 17 RF2 18 RH7 19 RH6 © 2009 Microchip Technology Inc. PIC18F872X FAMILY PIC18F8XXX RJ2 60 RJ3 59 RB0 58 RB1 57 RB2 56 RB3 55 RB4 54 RB5/PGM 53 RB6/PGC RA6 50 RA7 RB7/PGD 47 RC5 46 RC4 45 ...
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... Read ‘0’s IMPLEMENTATION OF CODE MEMORY Code Memory Size (Bytes) 000000h-00BFFFh (48K) 000000h-00FFFFh (64K) Address Range 000000h 0007FFh* or 000FFFh* or 001FFFh* 000800h* or 001000h* or 002000h* 003FFFh 004000h 007FFFh 008000h 00BFFFh 00C000h 00FFFFh 010000h 013FFFh 014000h 017FFFh 018000h 01BFFFh 01C000h 01FFFFh © 2009 Microchip Technology Inc. ...
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... Unimplemented Read as ‘0’ 200000h Configuration and ID Space 3FFFFFh Note: Sizes of memory areas are not to scale. * Boot Block size is determined by the BBSIZ<1:0> bits in CONFIG4L. © 2009 Microchip Technology Inc. PIC18F872X FAMILY TABLE 2-3: blocks. For Device PIC18F6627 PIC18F8627 PIC18F6628 PIC18F8628 PIC18F6722 ...
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... TBLPTRU, at RAM address 0FF8h • TBLPTRH, at RAM address 0FF7h • TBLPTRL, at RAM address 0FF6h TBLPTRU TBLPTRH Addr[21:16] Addr[15:8] The 4-bit command, ‘0000’ (core instruction), is used to load the Table Pointer prior to using many read or write operations. © 2009 Microchip Technology Inc. TBLPTRL Addr[7:0] ...
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... CONFIGURATION AND ID LOCATIONS FOR PIC18F872X FAMILY DEVICES 000000h Code Memory 01FFFFh Unimplemented Read as ‘0’ 1FFFFFh Configuration and ID Space 2FFFFFh 3FFFFFh Note: Sizes of memory areas are not to scale. © 2009 Microchip Technology Inc. PIC18F872X FAMILY ID Location 1 200000h ID Location 2 200001h ID Location 3 200002h ID Location 4 200003h ID Location 5 200004h ID Location 6 200005h ...
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... Verify mode places all unused I/Os in the high-impedance state. FIGURE 2-7: ENTERING HIGH-VOLTAGE PROGRAM/VERIFY MODE P13 P12 P1 D110 MCLR/V /RG5 PGD PGC PGD = Input FIGURE 2-8: EXITING HIGH-VOLTAGE PROGRAM/VERIFY MODE P16 P17 P1 MCLR/V /RG5 PP D110 V DD PGD PGC PGD = Input © 2009 Microchip Technology Inc. /RG5 to V IHH ...
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... PGM V IH PGD PGC PGD = Input © 2009 Microchip Technology Inc. PIC18F872X FAMILY 2.7 Serial Program/Verify Operation The PGC pin is used as a clock input pin and the PGD pin is used for entering command bits and data input/ output during serial operation. Commands and data are ...
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... PIC18F872X FAMILY FIGURE 2-11: TABLE WRITE, POST-INCREMENT TIMING (1101) P2 P2A P2B PGC PGD LSb MSb LSb 4-Bit Command DS39643C-page LSB MSB 16-Bit Data Payload PGD = Input P5A MSb 3 Fetch Next 4-Bit Command © 2009 Microchip Technology Inc. ...
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... Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2009 Microchip Technology Inc. PIC18F872X FAMILY The WREN bit must be set (EECON1<2> enable writes of any sort (e.g., erases) and this must be done prior to initiating a write sequence. The FREE bit must be set (EECON1< ...
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... MOVWF TBLPTRL 87 87 Write 87h TO 3C0004h to erase entire device. NOP 00 00 Hold PGD low until 00 00 erase completes. BULK ERASE FLOW Start Write 0Fh to 3C0005h Write 87h to 3C0004h to Erase Entire Device Delay P11 + P10 Time Done © 2009 Microchip Technology Inc. ...
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... Code Memory” determined that a data EEPROM erase must be performed at a supply voltage below the Bulk Erase limit, follow the methodology described in Section 3.3 “Data EEPROM Programming” and write ‘1’s to the array. © 2009 Microchip Technology Inc. PIC18F872X FAMILY ...
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... NOP – hold PGC high for time P9 and low for time P10. Start Configure Device for Row Erases Start Erase Sequence and Hold PGC High for Time P9 Hold PGC Low for Time P10 All No rows done? Yes Done Addr = 0 © 2009 Microchip Technology Inc. ...
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... Command 16-Bit Data Payload © 2009 Microchip Technology Inc. PIC18F872X FAMILY The code sequence to program a PIC18F872X family device is shown in Table 3-5. The flowchart, shown in Figure 3-6, depicts the logic necessary to completely write a PIC18F872X family device. The timing diagram that details the Start Programming command and parameters, P9 and P10, is shown in Figure 3-4 ...
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... PIC18F872X FAMILY FIGURE 3-5: ERASE AND WRITE BOUNDARIES Panel 2 TBLPTR<21:16> Offset = TBLPTR<15:6> Panel 1 TBLPTR<21:16> Offset = TBLPTR<15:6> Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL. DS39643C-page 16 TBLPTR<5:0> TBLPTR<5:0> TBLPTR<5:0> TBLPTR<5:0> Erase Region 64 bytes Erase Region 64 bytes © 2009 Microchip Technology Inc. ...
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... To continue writing data, repeat step 3, where the Address Pointer is incremented each iteration of the loop. © 2009 Microchip Technology Inc. PIC18F872X FAMILY Core Instruction BSF EECON1, EEPGD BSF EECON1, CFGS BSF EECON1, WREN BSF EECON1, EEPGD ...
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... LoopCount = LoopCount + 1 DS39643C-page 18 Start LoopCount = 0 Load 2 Bytes to Write Buffer at <Addr> All No bytes written? Yes Start Write Sequence and Hold PGC High until Done and Wait P9 Hold PGC Low for Time P10 All No locations done? Yes Done © 2009 Microchip Technology Inc. ...
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... To continue modifying data, repeat Steps 2 through 8, where the Address Pointer is incremented by the 64 bytes at each iteration of the loop. Step 9: Disable writes. 0000 94 A6 © 2009 Microchip Technology Inc. PIC18F872X FAMILY The appropriate number of bytes required for the erase buffer must be read out of code memory (as described in Section 4.2 “Verify Code Memory and ID Loca- tions” ...
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... MOVWF TABLAT PGD = Input PROGRAM DATA FLOW Start Set Address Set Data Enable Write Start Write Sequence No WR bit clear? Yes No Done? Yes Done P10 16-Bit Data Payload P5A Shift Out Data (see Figure 4-4) PGD = Output © 2009 Microchip Technology Inc. ...
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... Step 7: Hold PGC low for time, P10. Step 8: Disable writes. 0000 94 A6 Repeat steps 2 through 8 to write more data. Note 1: See Figure 4-4 for details on shift out data timing. © 2009 Microchip Technology Inc. PIC18F872X FAMILY Core Instruction BCF EECON1, EEPGD BCF EECON1, CFGS MOVLW < ...
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... MOVWF TBLPTRL Write 2 bytes and post-increment address by 2. Write 2 bytes and post-increment address by 2. Write 2 bytes and post-increment address by 2. Write 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. © 2009 Microchip Technology Inc. ...
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... Address Program LSB Delay P9 and P10 Time for Write Done © 2009 Microchip Technology Inc. PIC18F872X FAMILY 3.6 Configuration Bits Programming Unlike code memory, the Configuration bits are programmed a byte at a time. The Table Write, Begin Programming 4-bit command (‘1111’) is used, but only 8 bits of the following 16-bit payload will be written ...
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... B0 MOVLW B0h 0000 6E 9C MOVWF MEMCON 0000 0E 38 MOVLW 38h 0000 6E F8 MOVWF TBLPTRU 0000 0E 00 MOVLW 00h 0000 6E F7 MOVWF TBLPTRH 0000 0E 04 MOVLW 04h 0000 6E F6 MOVWF TBLPTRL 1100 70 70 Write 70h to 380004h © 2009 Microchip Technology Inc. ...
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... PGD = Input © 2009 Microchip Technology Inc. PIC18F872X FAMILY The 4-bit command is shifted in LSb first. The read is executed during the next 8 clocks, then shifted out on PGD during the last 8 clocks, LSb to MSb. A delay of P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output ...
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... Table Pointer back to 000000h, rather than point to unimplemented address, 020000h. Set TBLPTR = 200000h Increment Pointer Failure, Report Error No Read Low Byte with Post-Increment Read High Byte with Post-Increment Does No Word = Expect Failure, Data? Report Error Yes All ID locations verified? Yes Done © 2009 Microchip Technology Inc. ...
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... Step 4: Load data into the Serial Data Holding register. 0000 50 A8 0000 6E F5 0000 00 00 0010 <MSB><LSB> Note 1: The <LSB> is undefined. The <MSB> is the data. © 2009 Microchip Technology Inc. PIC18F872X FAMILY FIGURE 4-3: Core Instruction BCF EECON1, EEPGD BCF EECON1, CFGS MOVLW <Addr> MOVWF EEADR MOVLW <AddrH> ...
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... Section 4.2 “Verify Code Memory and ID Locations” for implementation details. DS39643C-page P14 3 4 LSb 1 2 Shift Data Out PGD = Output FIGURE 4-5: Blank Check Device P5A MSb Fetch Next 4-Bit Command PGD = Input BLANK CHECK FLOW Start Is Yes device Continue blank? No Abort © 2009 Microchip Technology Inc. ...
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... Implemented in 80-pin devices only. On 64-pin devices, these bits are reserved and should always be maintained as ‘1’ recommended to enable the corresponding CPx bit to protect blocks from external read operations. © 2009 Microchip Technology Inc. PIC18F872X FAMILY 5.1 ID Locations A user may store identification information (ID) in eight ID locations, mapped in 200000h:200007h ...
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... Read Low Byte with Post-Increment Read High Byte with Post-Increment Done DEVID1 010x xxxx 100x xxxx 110x xxxx 110x xxxx 000x xxxx 000x xxxx 011x xxxx 101x xxxx 111x xxxx 111x xxxx 001x xxxx 001x xxxx © 2009 Microchip Technology Inc. ...
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... Note 1: The BBSIZ<1:0> bits cannot be changed once any of the following code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0. 2: Available on PIC18F8XXX devices only. © 2009 Microchip Technology Inc. PIC18F872X FAMILY Description Internal External Switchover bit 1 = Internal External Switchover mode enabled ...
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... Reset on stack overflow/underflow enabled 0 = Reset on stack overflow/underflow disabled Code Protection bits (Block 7 code memory area Block 7 is not code-protected 0 = Block 7 is code-protected Code Protection bits (Block 6 code memory area Block 6 is not code-protected 0 = Block 6 is code-protected © 2009 Microchip Technology Inc. ...
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... The BBSIZ<1:0> bits cannot be changed once any of the following code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0. 2: Available on PIC18F8XXX devices only. © 2009 Microchip Technology Inc. PIC18F872X FAMILY Description Code Protection bits (Block 5 code memory area Block 5 is not code-protected ...
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... These bits are used with the DEV<2:0> bits in the DEVID1 register to identify the part number. Device ID bits These bits are used with the DEV<10:3> bits in the DEVID2 register to identify the part number. Revision ID bits These bits are used to indicate the revision of the device. © 2009 Microchip Technology Inc. ...
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... EEPROM information may be provided. When embedding data EEPROM information . Once IHH in the hex file, it should start at address, F00000h. Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. 5.6 Checksum Computation to the MCLR/ The checksum is calculated by summing the following: • ...
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... Description CFGW = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND DS39643C-page 36 Checksum © 2009 Microchip Technology Inc. 0xAA at 0 Blank and Max Value Address 4340h 4296h 4B78h 4B23h C375h C320h ...
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... Item Description CFGW = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND © 2009 Microchip Technology Inc. PIC18F872X FAMILY Checksum 0xAA at 0 Blank and Max Value Address 83E8h 833Eh 8C20h 8BCBh ...
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... Description CFGW = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND DS39643C-page 38 Checksum © 2009 Microchip Technology Inc. 0xAA at 0 Blank and Max Value Address 4435h 438Bh 4C6Dh 4C18h C46Ah C415h ...
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... Item Description CFGW = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND © 2009 Microchip Technology Inc. PIC18F872X FAMILY Checksum 0xAA at 0 Blank and Max Value Address 84DDh 8433h 8D15h 8CC0h ...
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... LP, HS, HS/PLL and XT modes only) + OSC is the Power-up Timer period and T PWRT Units Conditions Self-timed V Externally timed V Bulk Erase operations μ meet AC specifications μs (Note 5.0V DD μ Externally timed μ μ the oscillator period. For OSC © 2009 Microchip Technology Inc. ...
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... HS/PLL mode only) + 1.5 μs (for EC mode only) where T is the instruction cycle time specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device. © 2009 Microchip Technology Inc. PIC18F872X FAMILY Min 10 /RG5 ↑ ...
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... PIC18F872X FAMILY NOTES: DS39643C-page 42 © 2009 Microchip Technology Inc. ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2009 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...