PIC24F08KA101T-I/SS Microchip Technology, PIC24F08KA101T-I/SS Datasheet - Page 10

• Manufacturer Part Number: PIC24F08KA101T-I/SS
• Description: 8KB Flash, 1KB RAM, 512B EEPROM, 16 MIPS, 16 I/O,16-bit PIC24F Family, NanoWatt
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F08KA101T-I/SS

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 8KB (2.75K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC24F16KA102 FAMILY
7. Module: Comparators
REGISTER 23-2:
8. Module: Pin Diagrams
DS80473F-page 10
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
CMIDL
R/W-0
The descriptions given for the CMIDL bit
(CMSTAT<15>) are incorrect. The correct
descriptions are shown below (changes in bold).
In many places in the data sheet, the UART
Baud Clock output functions, U1BCLK and
U2BCLK, are shown as being multiplexed on the
same pins as the UART Receive input functions
(U1RX and U2RX). The Baud Clock is actually
multiplexed with the UART Ready-to-Send out-
put function (U1RTS and U2RTS) on completely
different pins. This mapping is correctly
described in the UART chapter, but incorrectly
shown on pin diagrams and pin function listings.
The pin diagrams from the data sheet are
replaced by the pin diagrams shown in
Figure 2
bold. Footnotes present in the original diagrams
have been omitted here for clarity.
In addition,
amended as shown. Footnotes in the original
table have been omitted for clarity. Changes are
indicated in bold.
U-0
—
and
CMIDL: Stop in Idle Mode bit
1 = Disable comparator interrupts when the device enters Idle mode; the module is still enabled
0 = Continue normal module operation in Idle mode
Table 1-2
Figure
U-0
U-0
—
—
CMSTAT: COMPARATOR MODULE STATUS REGISTER
3. Changes are noted in
of the device data sheet is
HSC = Hardware Settable/Clearable bit
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
Figure
U-0
U-0
1,
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
U-0
U-0
—
—
 2010 Microchip Technology Inc.
x = Bit is unknown
R-0, HSC
R-0, HSC
C2OUT
C2EVT
R-0, HSC
R-0, HSC
C1OUT
C1EVT
bit 8
bit 0