PIC24F16KA101T-I/SS Microchip Technology, PIC24F16KA101T-I/SS Datasheet - Page 54
![16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 16 I/O,16-bit PIC24F Family, NanoWatt](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC24F16KA101T-I/SS
Manufacturer Part Number
PIC24F16KA101T-I/SS
Description
16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 16 I/O,16-bit PIC24F Family, NanoWatt
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.MA240017.pdf
(254 pages)
2.PIC24F04KA201-ISS.pdf
(48 pages)
3.PIC24F16KA101-ISS.pdf
(18 pages)
Specifications of PIC24F16KA101T-I/SS
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
16KB (5.5K x 24)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24F16KA101T-I/SS
Manufacturer:
MICROCHIR
Quantity:
20 000
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PIC24F16KA102 FAMILY
REGISTER 6-1:
DS39927B-page 52
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11-7
bit 6
bit 5-0
R/S-0, HC
WR
U-0
—
WR: Write Control bit (program or erase)
1 = Initiates a data EEPROM erase or write cycle (can be set but not cleared in software)
0 = Write cycle is complete (cleared automatically by hardware)
WREN: Write Enable bit (erase or program)
1 = Enable an erase or program operation
0 = No operation allowed (device clears this bit on completion of the write/erase operation)
WRERR: Flash Error Flag bit
1 = A write operation is prematurely terminated (any MCLR or WDT Reset during programming
0 = The write operation completed successfully
PGMONLY: Program Only Enable bit
1 = Write operation is executed without erasing target address(es) first
0 = Automatic erase-before-write: write operations are preceded automatically by an erase of target
Unimplemented: Read as ‘0’
ERASE: Erase Operation Select bit
1 = Perform an erase operation when WR is set
0 = Perform a write operation when WR is set
NVMOP<5:0>: Programming Operation Command Byte bits
Erase Operations (when ERASE bit is ‘1’):
011010 = Erase 8 words
011001 = Erase 4 words
011000 = Erase 1 word
0100xx = Erase entire data EEPROM
Programming Operations (when ERASE bit is ‘0’):
001xx = Write 1 word
ERASE
WREN
R/W-0
R/W-0
operation)
address(es)
NVMCON: NONVOLATILE MEMORY CONTROL REGISTER
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
NVMOP5
WRERR
R/W-0
R/W-0
PGMONLY
NVMOP4
R/W-0
R/W-0
Preliminary
S = Settable bit
‘0’ = Bit is cleared
NVMOP3
R/W-0
U-0
—
NVMOP2
R/W-0
U-0
—
HC = Hardware Clearable bit
x = Bit is unknown
© 2009 Microchip Technology Inc.
NVMOP1
R/W-0
U-0
—
NVMOP0
R/W-0
U-0
—
bit 8
bit 0
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